A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating calibration, and the clock is subsequently gated to save power during idle. The QEC, controlled digitally by an FSM, features chopping cancellation to eliminate DC offset and device mismatches. The DCC and QEC achieve less than 0.3% duty cycle error and 330fs quadrature phase error.

📋 论文概要

该论文提出了一种符合UCIe标准的低延迟接口，采用3nm工艺，通过匹配延迟架构实现动态时钟门控，避免了传统时钟前导码带来的额外延迟，在32Gb/s速率下达到10.5Tb/s/mm的带宽密度和0.6pJ/b的能效。

💡 主要创新点

• 提出匹配延迟架构用于动态时钟门控，确保取消门控后的第一个时钟沿能正确捕获数据，无附加延迟。
• 实现了UCIe兼容接口的高带宽密度（10.5Tb/s/mm）和低能耗（0.6pJ/b），采用先进3nm工艺。

🏷 关键词

📄 原文摘要

Wen-Hung Huang1, Yu-Chi Chen1, Yu-Jie Huang1, Alan Drake3, Chin-Hua Wen1, Paul Ranucci3, Hsin-Hung Kuo1, Aidong Yin3, Shu-Chun Yang1, Farsheed Mahmoudi3, Han-Tzung Ke1, Chao-Chieh Li1, Nai-Chen Cheng1, Jimmy Wang4, Kevin Lin1, Harry Liao4, Jie-Ren Huang1, Meng-Hsuan Wu4, Kenny Cheng-Hsiang Hsieh1, Nicholas Amatruda5, William Polanco5, David King5, Todd Basso6, Anwar Kashem6 A matched-delay architecture is vital for dynamic clock gating to ensure that the first clock transition after un-gating captures data correctly without added latency from a clock preamble. The receiver’s DCC/QEC must be digital to support instant mission-mode operation. The challenge is exacerbated when rapid Di/Dt induces significant dynamic voltage droop on the power rail, which cannot be recovered through clock preamble and exceeds the receiver-side DLL’s tracking capability at 32Gb/s. This necessitates a well-matched forwarded clock architecture. Figure 36.1.4 illustrates the receiver architecture

👥 作者与机构

Mu-Shan Lin1, Chien-Chun Tsai1, Shenggao Li2, Wei-Chih Chen1,