⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种10位3GS/s的时间域模数转换器（TD ADC），通过互斥亚稳态校正技术解决了时间域ADC在严格时间限制下严重的亚稳态问题，并实现了宽共模输入范围。该设计适用于低误码率串行链路接收器、雷达和仪器仪表等应用。
unpredictable and non-Gaussian error behaviors in the A/D conversion, which cannot be tolerated by applications such as lowbit-error-rate serial link receivers, radar, and instrumentation [1-5]. Time-domain (TD) ADCs [6-11] have demonstrated a superior speed to their voltage-domain (VD) SAR and pipeline counterparts thanks to the technology scaling. However, the metastability artifact of the TD ADC is often overlooked, which can be severe under a stringent time deadline and is worth great attention. In literature, TD circuits are often leveraged to facilitate the “metastability detector” [1], while the metastability events indeed cannot be detected because the detector itself can experience metastability. They often detect the error within the loop time, which
Zijian Liu1, Minglei Zhang1, Wei Zhang1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Metastable trajectories in comparators pose