A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration

📋 论文概要

提出了一种12位3GS/s流水线ADC，采用基于门控LMS算法的分段线性非线性校准技术，解决了开环残差放大器引起的增益误差和严重非线性问题。该校准方法在后台通过dither注入和门控LMS自适应更新校准系数，相比传统多项式校准具有更低复杂度。

💡 主要创新点

• 首次将门控LMS算法应用于流水线ADC的分段线性非线性校准，实现高效的背景校准。
• 采用分段线性逼近代替多项式拟合非线性，降低了校准复杂度并提高了收敛速度。
• 在12位3GS/s的高速流水线ADC中实现了有效非线性校正，同时保持了高能效和高速度优势。

🏷 关键词

📄 原文摘要

The pipelined ADC is an attractive choice for high-speed and high-resolution applications. Its most important building block is the residue amplifier. Compared with conventional closed-loop amplifiers, open-loop amplifiers are advantageous in speed, energy efficiency, design simplicity, and scaling friendliness [1]. However, they suffer from large gain errors and severe gain nonlinearity. Addressing these nonidealities conventionally requires polynomial-based calibration [1]-[3]. Although the calibration coefficients can be easily extracted in the background through dither injection and gated LMS filters [3], the polynomial computation introduces significant power and area overhead, especially at sampling rates over 1GS/s. The piecewise-linear (PWL) nonlinearity calibration scheme is an attractive alternative to reduce the computational complexity [4]. However, existing PWL calibration techniques extract the calibration coefficients in the foreground with large analog

👥 作者与机构

Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun

Tsinghua University, Beijing, China