A 12.2µW 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD ∆ΣM with Gain-Embedded Bootstrapped Sampler

📋 论文概要

本文提出一种12.2µW功耗、99.6dB SNDR、184.8dB FOMS的离散时间Zoom PPD ΔΣ调制器，采用增益嵌入式自举采样器。该设计解决了传统离散时间ΔΣ调制器因大采样电容导致输入缓冲器驱动负担大的问题，实现了超低功耗高精度转换。

💡 主要创新点

• 提出增益嵌入式自举采样器，在不增加额外功耗的情况下提高采样线性度和增益，降低对输入缓冲器的驱动要求。
• 采用Zoom PPD（预测路径驱动）架构，结合离散时间ΔΣ调制，实现极低功耗下的高精度（99.6dB SNDR）。

🏷 关键词

📄 原文摘要

consumption as they determine the overall noise and linearity performance. To achieve high resolution, discrete-time (DT) ∆ΣMs require large sampling capacitors [1-3]. This induces a huge driving burden for the ADC input buffer to satisfy settling requirements, which follows an exponential curve and requires a large current to be drawn (Fig. 18.2.1). This is addressed by CT-∆ΣM architecture where the input driver only sees resistive input [4-10]. While the input current is proportional to the large voltage signal Vin, most of it is wasted through the RDAC. Only the residue signal Iin-IDAC is effectively integrated into the later stage. Like its DT counterpart, CT-∆ΣM also suffers from passive noise contributed by resistors. The continuous-time CDAC input stage avoids this problem [11-13], but noisy CDAC switching

👥 作者与机构

Yaohui Luan, Xinhang Xu, Jihang Gao, Jiajia Cui, Zhuoyi Chen, Siyuan Ye,

Ru Huang, Linxiao Shen Peking University, Beijing, China Input stages involving a 1st integrator and feedback DAC dominate ∆ΣM power