A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting

📋 论文概要

该论文提出了一种轨到轨三阶噪声整形SAR ADC，集成了连续时间输入缓冲器，解决了高分辨率SAR ADC中CDAC负载大、输入缓冲器驱动压力高和线性度要求苛刻的问题，实现了105.4dB的无杂散动态范围（SFDR）。

💡 主要创新点

• 提出轨到轨输入缓冲器与连续时间结构集成，避免单独高压电源，降低功耗并提高线性度。
• 采用三阶噪声整形技术，有效抑制带内噪声，提升高分辨率SAR ADC的SFDR。

🏷 关键词

📄 原文摘要

With the development of high-resolution ADCs (>13b) leveraging the SAR topology, the pursuit of power efficiency in ADC design continues to make remarkable strides [1-5]. However, as the capacitance of the capacitive DAC (CDAC) increases to satisfy the kT/C noise specification, excessive driving pressure is posed on the front-end input buffer. Furthermore, a separate higher supply voltage is typically demanded for the driver to accommodate the input swing while maintaining the linearity requirement. The increasing load and wide supply voltage often make the power consumption of the ADC core overwhelmed by the power consumption of the driving buffer, presenting a bottleneck in achieving an overall energy-efficient system. Loop-embedded buffer architectures have been explored in prior arts to reduce the linearity requirement of the buffer while easing the driving pressure of the system [2], [6-8]. Rail-to-rail signal swing is achieved in [7] with a

👥 作者与机构

Siyuan Ye, Jiajia Cui, Jihang Gao, Jie Li, Xing Zhang, Ru Huang, Linxiao Shen

Peking University, Beijing, China