⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种采用2nm CMOS纳米片技术的高密度SRAM，实现了38.1 Mb/mm²的存储密度，旨在满足高容量片上存储需求并提升能效。通过优化位单元面积和工艺缩放，解决了先进节点下嵌入式存储器的密度与功耗挑战。
Teja Masina, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Ku-Feng Lin, Ming-Hung Chang, Ching Wei Wu, Robin Lee, Yih Wang, Hung-Jen Liao, Quincy Li, Ping Wei Wang, Geoffrey Yeap TSMC, Hsinchu, Taiwan Embedded memories are crucial SoC design components; among these, SRAM plays a vital role in enhancing system performance across various applications. The ongoing demand for high-capacity on-die SRAM necessitates optimal-density scaling as we transition technology nodes. In mature technology nodes, reducing the bit cell area significantly contributed to SRAM scaling. However, as we move into more advanced technology nodes, scaling the cell area becomes increasingly challenging. Design-technology co-optimization (DTCO) becomes essential to achieving further area scaling at the chip level. We focus on optimizing both cell and peripheral designs to improve memory density. Our SRAM design
Tsung-Yung Jonathan Chang, Yen-Huei Chen, K. Venkateswara Reddy, Nikhil Puri,