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ISSCC 2025Session 27 · SENSOR INTERFACESRF & Wireless

A Voltage-Biased CMOS Hall Sensor with 1.0µT (3σ) Offset and a 60nT/√Hz Noise-Floor

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📋 论文概要

本文提出一种电压偏置的CMOS霍尔传感器,通过将传统电流偏置电压输出改为电压偏置电流输出,显著降低了传感器的失调和噪声。实现了1.0µT (3σ)的失调和60nT/√Hz的噪声底,优于传统结构。

💡 主要创新点

核心指标
1.0µT (3σ) offset, 60nT/√Hz noise floor
重要性
发表年份
ISSCC 2025

🏷 关键词

霍尔传感器电压偏置失调降低CMOS低噪声

📄 原文摘要

Tsinghua University, Beijing, China 1 2 Hall sensors are the only CMOS devices capable of measuring DC magnetic fields and so they are used in a wide range of applications, such as in compasses and current sensors. In such applications, their Achilles heel is their offset, which is typically in the order of several (tens of) µT [1-3]. Conventionally, Hall sensors are biased by current sources and output voltages that are proportional to an external magnetic field. In this work, a dual arrangement is proposed, in which a Hall sensor is biased by a voltage source and outputs a current. In a standard 0.18µm CMOS process, a prototype Hall sensor with a low-offset readout circuit achieves an offset of 1.0µT(3σ) with a noise floor of 60nT/√Hz. Compared to the state-of-the-art [1], this represents a 3$ reduction in offset and a 5$ improvement in resolution. As shown in Fig. 27.2.1 (left), a typical CMOS Hall sensor consists of an n-well plate, which

👥 作者与机构

Floris J. P. van Mourik1, Sining Pan2, Karen M. Dowling1, Kofi A. A. Makinwa1

TU Delft, Delft, The Netherlands

分类:RF & Wireless · 年份:ISSCC 2025