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ISSCC 2025Session 14 · COMPUTE-IN-MEMORYAI / ML28nm

A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer

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📋 论文概要

该论文提出了一种28nm工艺的64kb位旋转混合域计算存储(CIM)宏,通过嵌入式符号位处理阵列和多比特融合双粒度技术,解决了混合域CIM中数字与模拟部分边界定义等挑战,实现了高效的计算存储。

💡 主要创新点

工艺节点
28nm
重要性
发表年份
ISSCC 2025

🏷 关键词

混合域计算存储位旋转符号位处理多比特融合双粒度

📄 原文摘要

Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si Southeast University, Nanjing, China Hybrid-domain CIMs [1-3] are attracting increasing attention nowadays as they combine the advantages of both digital CIMs (DCIM) [4-6] and analog CIMs (ACIM) [7-10], offering a more balanced choice. As depicted in Figure 14.6.1, when designing a hybrid CIM (HCIM), the first challenge to address is (1) the definition of boundary between the digital and analog part, which is determined by feature input mode and weight mapping. Prior HCIMs either utilized a bit-parallel in features to obtain high accuracy at the cost of hardware (HW) overhead [1] or realized a low HW overhead but suffered from accuracy loss due to error pollution problem (error of the analog partial sum makes the high precision digital partial

👥 作者与机构

Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang,

分类:AI / ML · 年份:ISSCC 2025