⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种基于3nm FinFET工艺和2.5D CoWoS封装的UCIe高级封装链路，实现了0.29pJ/b的能效和5.27Tb/s/mm的带宽密度，解决了异构集成中高带宽、低功耗互连的挑战。
Prakash BS2, Adrian Leuciuc4, Kevin Geary5, Shaojun Ma1, Chirag Mukesh Mehta1, Basant Bothra2, Shashi Jain2, Pawan Sabharwal6, Ranjan Vaish1, Kirti Bhanushali3, Yutong Ding7, Craig Frost4, John Annunziata4, Krishanu Sadhu6, Dimitris Kyritsis5, Jeff Bostak1, Ming Li7, Steve Williams4, Ken Chang8 Cadence, San Jose, CA Cadence, Bangalore, India 3 Cadence, Cary, NC 4 Cadence, Columbia, MD 5 Cadence, Cork, Ireland 6 Cadence, Noida, India 7 Cadence, Nanjing, China 8 now with Marvell, Santa Clara, CA 1 2 Advances in packaging technologies have accelerated heterogenous disaggregation of SoCs by enabling the integration of IPs in different technology nodes within a single package. Such systems-in-package (SiP) require highly bandwidth-efficient, low-power die-to-die (D2D) links with low latency and BER. The Universal Chiplet Interconnect Express (UCIe) standard [1] offers a blueprint on building D2D links that provide solutions to these
Didem Turker Melek1, R. NavinKumar2, James Vandersand3, Pyare Sarkar2,