A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme

📋 论文概要

该论文提出了一种在3nm工艺下实现的3.6GHz双端口SRAM，通过后端RC优化和远端写辅助方案解决了高频操作下的设计复杂性和写裕度问题。实现了同时读写操作和异步时钟域的高带宽通信。

💡 主要创新点

• 采用后端RC优化技术减少互连线延迟和功耗，提升高速性能。
• 提出远端写辅助方案，改善远离写驱动器的存储单元写裕度。
• 在3nm先进工艺节点下实现了3.6GHz的高频率操作。

🏷 关键词

📄 原文摘要

Cheng-Han Lin1, Shan-Ru Liao1, Kenta Torigoe2, Shirleen Xia3, Yuichiro Ishii3, Yao-Yi Liu1, Jhon-Jhy Liaw1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonathan Chang1 TSMC, Hsinchu, Taiwan TSMC Design Technology Japan, Osaka, Japan 3 TSMC Design Technology Japan, Yokohama, Japan 1 2 Dual-port (DP) SRAM offer simultaneous read and write operation with two asynchronous clocks, and can realize higher read and write bandwidth from two different clock frequency domains [1-5]. However, design complexity is higher than for a single-port (SP) SRAM, when considering worst-case operation. In addition, resistance degradation, caused by process scaling, becomes more severe in leading-edge technology nodes, we must consider resistance and capacitance (RC) impact in the circuit design. In this paper, we report a 20kb DP-SRAM in a 3nm process technology with a 0.052µm2 DP-SRAM cell. Increased designtechnology co-optimization (DTCO) opportunities in the DP-SRAM cell and its peripheral

👥 作者与机构

Hidehiro Fujiwara1, Wei-Chang Zhao1, Kinshuk Khare1, Yi-Hsin Nien1, Chih-Yu Lin1,