A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplifier with a Stacked OPA-Based Bias Scheme Achieving >16.5dBm Pavg for 5G FR2 Applications

📋 论文概要

该论文在22nm FDSOI CMOS工艺上设计了一种紧凑的3级堆叠Doherty功率放大器，通过堆叠OPA偏置方案，实现了超过16.5dBm的输出功率，适用于毫米波相控阵系统。

💡 主要创新点

• 采用3级堆叠Doherty结构在22nm FDSOI上实现紧凑毫米波PA设计，提升集成度。
• 提出堆叠运算放大器(OPA)偏置方案，改善PA的线性度和效率。

🏷 关键词

📄 原文摘要

interest in the millimeter-wave (mm-wave) band. In this frequency range, phased-array systems are crucial for sustaining communication performance despite high propagation loss. In highly integrated phased-array systems, multiple power amplifiers (PAs) need to be integrated within a transceiver chip, requiring compact PA designs. As a result, silicon-based CMOS technology offers benefits in terms of miniaturization and integration, making it appropriate for phased-array-system PAs. Meanwhile, emerging applications, such as fixed wireless access (FWA), require an equivalent isotropic radiated power (EIRP) of over 70dBm, necessitating an increase in PA output power. Moreover, 5G new-radio (NR) orthogonalfrequency-division-multiplexing (OFDM) systems exhibit peak-to-average power ratios

👥 作者与机构

Jooseok Lee, Hansik Oh, Seungjae Baek, Seungwon Park, Dongsoo Lee,

Sehyug Jeon, Taewan Kim, Joonho Jung, Sung-gi Yang Samsung Electronics, Seoul, Korea The increasing demand for wireless communication has generated significant