A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process

📋 论文概要

本文提出一款16Gb容量、12.7Gb/s/pin速率的LPDDR5-Ultra-Pro DRAM，采用4-phase自校准技术和AC耦合收发器均衡，解决了高速数据传输中的信号完整性挑战。

💡 主要创新点

• 采用4-phase自校准技术，提高时序精度和可靠性。
• 引入AC耦合收发器均衡，改善高频信号传输质量。

🏷 关键词

📄 原文摘要

Jin-Kwan Park, Hyun-Kyu Oh, Bo-Hyeon Lee, Dong-Wan Ko, Tae-Seob Oh, Seung-Gi Hong, Chang-Ki Kwon, Daihyun Lim, Myeong-O Kim, Seung-Jun Bae, Tae-Young Oh, Sang-Jun Hwang Samsung Electronics, Hwaseong, Korea The rapid growth of AI, AR, and VR applications has increased demand for high-speed data processing and high-density low-power memory modules. LPDDR5X has played an important role in meeting these demands [1]. LPDDR5X introduced optional JEDEC features, such as per-pin decision-feedback equalizers (DFE), offset calibration, pre-emphasis transmitters, and read duty-cycle adjusters (RDCA) [2], to enhance IO performance; however, LPDDR5X faces various speed-requirement challenges. Recently, there has been a strong demand for high-speed operation beyond 10.7Gb/s/pin; the low-power compression-attached memory module 2 (LPCAMM2) for servers has emerged to address this low-power high-capacity requirement. To achieve sufficient IO timing margins, using

👥 作者与机构

Jin-Hyeok Baek, Jang-Hoo Kim, Yoo-Chang Sung, Jae-Woo Jeong,