A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding

📋 论文概要

该论文提出了一种32-50Gb/s/pin单端PAM-4发射机，采用基于ZQ校准的前馈均衡（FFE）和PAM-4最低有效位数据总线反转直流平衡编码（LSB DBI-DC），以提升内存接口带宽和抗噪性能。

💡 主要创新点

• 提出ZQ-Based FFE，利用阻抗校准网络实现均衡，降低面积和功耗。
• 提出PAM-4 LSB DBI-DC编码，在保持直流平衡的同时减少信号跳变，提高信噪比。

🏷 关键词

📄 原文摘要

demand for data processing and transmission has surged: highlighting the need for high-speed and energy-efficient data transmission between processors and memory. While data processing capabilities continue to advance, the memory-interface bandwidth has struggled to keep up; primarily limited by channel bandwidth and noise-susceptibility of single-ended signaling, which is commonly used for memory interfaces. One promising approach to overcome channel-bandwidth limitation is multi-level pulse amplitude modulation (PAMn), which increases the bit rate without increasing the baud rate, at the cost of increased (n) signaling levels. PAMn has been widely adopted for recent memory interfaces, such as PAM4 for GDDR6X [1,2] and PAM3 for GDDR7 [3,4]. However, the reduced signal-level spacing, 1/2 for PAM3 and 1/3 for PAM4,

👥 作者与机构

Yunseong Jo*1, Hyuntae Kim*1, Young Choi2, Jaewoo Park2, Myoungbo Kwak2, Jaeduk Han1

Hanyang University, Seoul, Korea Samsung Electronics, Hwaseong, Korea 1 2 *Equally Credited Authors (ECAs) With the rapid growth of the AI industry,