A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a 0.001681μm2 1T-1MTJ Cross-Point Cell

📋 论文概要

该论文提出了一种时间控制放电读取方案，实现了64Gb容量的DDR4 STT-MRAM，采用0.001681μm²的1T-1MTJ交叉点单元，旨在满足AI、数据库等应用对高密度、低延迟存储级内存的需求。

💡 主要创新点

• 提出时间控制放电读取（Time-Controlled Discharge-Reading）方案，优化STT-MRAM的读取路径与时序，降低读取延迟并提高可靠性。
• 实现了极小的0.001681μm² 1T-1MTJ交叉点单元，显著提升存储密度，达到64Gb容量。
• 兼容DDR4接口，使MRAM可直接替代传统DRAM，适用于高性能计算与存储级内存场景。

🏷 关键词

📄 原文摘要

Takaya Yasuda1, Akira Katayama1, Tadashi Miyakawa1, Kazuyo Senju1, Kazuki Okawa1, Yuka Furukawa1, Yu Shimada1, Katsuya Kotake1, Sayaka Hirokawa1, Min Chul Shin2, Dong Keun Kim2, Tae Ho Kim2, Kyunghoon Kim2, Hisanori Aikawa3, Jeonghwan Song2, Toshihiko Nagase3, Soo Man Seo2, Soo Gil Kim2, Seon Yong Cha2 KIOXIA, Yokohama, Japan SK hynix, Icheon, Korea 3 KIOXIA Korea, Seoul, Korea 1 2 Recent and rapid demands for new applications such as AI, database processing, big-data processing, and real-time applications have enhanced development of storage-class memories (SCM) targeting high density, low latency and high reliability. Meanwhile, MRAM technologies have been widely commercialized as eMRAM and stand-alone MRAM [1-4], but they have insufficient density for SCM applications. A narrow-pitch 1-selector and 1-MTJ (1S1M) cell that enhances the MRAM bit density has been previously reported [5,9].

👥 作者与机构

Kosuke Hatsuda1, Katsuhiko Hoya1, Ryousuke Takizawa1, Fumiyoshi Matsuoka1,