A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver

📋 论文概要

本文提出了一种基于时钟参考的PAM3收发器，用于解决芯片间接口中单端PAM3信令面临的参考电压生成面积大、收发参考匹配困难等问题，实现了0.275pJ/b的能效和42Gb/s/pin的数据速率。

💡 主要创新点

• 采用时钟参考代替传统参考电压生成器，消除了大面积Vrefp/Vrefn发生器，降低了面积和功耗。
• 通过时钟参考技术改善收发器参考匹配，增强对电源噪声、参考偏移和串扰的容忍性。

🏷 关键词

📄 原文摘要

multi-chip modules (MCMs), die-to-die (D2D), and chiplet interfaces (e.g. UCIe) requires high-bandwidth densities while minimizing power consumption [1,3,4,11-13]. Single-ended (SE) PAM3 signaling has been adopted in GDDR7 [2] as a high-bandwidth solution, increasing the data rate by 150%, compared to NRZ (PAM2) using the same baud rate. SE PAM3 signaling can also be applied to chiplet interfaces, but it faces challenges (Fig. 22.1.1): (1) the RX requires large-area reference-voltage (Vrefp & Vrefn) generators. (2) Matching RX and TX references is challenging, and discrepancies result in a TX-RX reference offset. (3) TX drivers generate simultaneous switching noise (SSN) of up to a few hundred millivolts on VDD in TX die [3]; this noise coupled to TX data and cannot be rejected by the

👥 作者与机构

Tolerant to Supply Noise, Reference Offset and Crosstalk for, Chiplets and Short-Reach Memory Interfaces

Kahyun Kim1, Jung-Hun Park2, Ha-Jung Park1, Jia Park1, Jihee Kim1, Woo-Seok Choi1 Seoul National University, Seoul, Korea University of California, Berkeley, CA 1 2 The trend of