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ISSCC 2025Session 22 · MEMORY INTERFACEMemory

A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces

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📋 论文概要

该论文提出了一种用于GDDR7内存接口的42Gb/s单端混合判决反馈均衡(DFE)PAM-3接收机。通过采用混合DFE架构,解决了高速PAM-3信号在内存接口中的均衡问题,实现了高数据率传输。

💡 主要创新点

核心指标
42Gb/s
重要性
发表年份
ISSCC 2025

🏷 关键词

GDDR7PAM-3混合DFE接收机

📄 原文摘要

Changhyun Pyo1, Seulgi Kim1, Byungjun Kang1, Eunji Song1, Kwangjin Na1, Jinyoup Cha1, Hyesoo Kim1, Shinyoung Park1, Woo-Seok Choi2, Kyunghoon Kim1, Hae-Kang Jung1, Joohwan Cho1, Jonghwan Kim1 SK hynix, Icheon, Korea Seoul National University, Seoul, Korea 1 2 *Equally Credited Authors (ECAs) Demand for high-bandwidth graphics memory is rapidly increasing for various applications such as AI, deep learning, autonomous cars, etc. To meet this demand, GDDR6X uses multi-level signaling (PAM4) for the first time in DRAM [1], while GDDR7 targets data-rates 28Gb/s or higher using PAM3 signaling. However, the increased data rate incurs higher inter-symbol interference (ISI), while PAM3 is more vulnerable to ISI than PAM2 signaling. Decision feedback equalizers (DFEs) are widely used in receivers (RX) to remove post-cursor ISI without amplifying noise. A PAM3 RX, with an analog DFE, typically employs

👥 作者与机构

Boram Kim*1, Hankyu Chi*1, Hyeongjun Ko1, Sangyeon Byeon1, Sungkwon Lee1,

分类:Memory · 年份:ISSCC 2025