A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR

📋 论文概要

本文提出了一种用于量子比特读出的低温CMOS SAR ADC，采用电荷注入（CI）结构，在800MS/s采样率下实现7位分辨率，输入电容仅4fF，SFDR达64dB。该设计旨在降低功耗以满足大规模量子计算的需求。

💡 主要创新点

• 采用电荷注入SAR架构（CI-SAR）实现极低输入电容（4fF），有利于降低量子读出电路的负载。
• 在低温环境下（cryo-CMOS）实现高速（800MS/s）中分辨率（7位）ADC，兼顾功耗与性能。

🏷 关键词

📄 原文摘要

Cryo-CMOS has shown great potential to implement fast, scalable and efficient readout circuits for quantum bits (qubits). Several cryo-CMOS circuits for the dispersive readout of transmon qubits [1-2] or the reflectometry and gate-based readout of spin qubits [3-6] have been presented in the literature. However, despite recent progress, their power consumption, ranging from 10mW to 108mW, remains too high to integrate the millions of qubits required for large-scale quantum computing [7]. On the other hand, prior art cryoCMOS SAR ADCs [8-11] show a power consumption ranging from 1.8mW to 10mW, which is only ~10% of the power budget of the full readout circuit. Most of the power is consumed by the analog front-end (LNA, mixer, filters) to pre-process the sensitive qubit signals and to drive the ADC [12]. Therefore, this work aims to lower the readout system power consumption by reducing the ADC driver requirements. An easy-to-drive 7b cryo-CMOS

👥 作者与机构

Bram Veraverbeke, Filip Tavernier

KU Leuven ESAT-MICAS, Leuven, Belgium