A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC

📋 论文概要

本文提出了一款采用4nm工艺的12位16GS/s自校准分层时间交织ADC，通过预采样技术和优化的时钟策略实现了高能效和小面积。解决了高速高精度ADC中功耗与面积权衡的问题。

💡 主要创新点

• 采用分层时间交织架构，结合预采样技术，有效降低子ADC的采集时间要求。
• 通过自校准技术补偿失配误差，提升整体线性度和动态性能。
• 优化4相时钟策略，在3Ts采集时间内完成子ADC操作，实现高吞吐率。

🏷 关键词

📄 原文摘要

Tsun-Yuan Fan1, Alec Chin1, Tsung-Chih Hung1, Jonathan X Wu2, Chi-Lun Lo2, Andy Pan1, Ming-Hang Hsieh1, Yun-Shiang Shu1, Wei-Hsin Tseng1, Kuan-Dar Chen1 MediaTek, Hsinchu, Taiwan MediaTek, Woburn, MA 1 Each sub-ADC, clocked at fs/16, is a pipeline-SAR hybrid with five pipelined 1.5b/stage MDACs, employing the pre-sampling technique [9], followed by a 7b SAR. For each THA driving four sub-ADCs, the above 4-phase clock strategy could apply with a 3Ts sub-ADC acquisition time and a long 13Ts conversion phase. But transistor-level simulations show diminishing relative benefits. Instead, the MDAC amplifiers are time-shared between pairs of sub-ADCs, as in Fig. 24.6.2. That is, they are 2× interleaved, clocking at fs/8, while the back-end quantizer 7b SARs (SAR-A, SAR-B) are individually clocked at fs/16 without sharing. For 7b resolution, a SAR back-end provides a moderate capacitive loading to the

👥 作者与机构

Cheng-En Hsieh*1, Gabriele Manganaro*2, Sheng-Hui Liao*1, Jack Weng*1,