A 0.3pJ/b 32Gb/s/pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer

📋 论文概要

该论文提出了一种采用无延迟电容反馈均衡器（CFE）的32Gb/s/pin单端PAM-4接收器，解决了多级信令低信噪比导致的复杂均衡问题。通过创新均衡器设计，在28nm CMOS工艺下实现了0.3pJ/b的高能效和0.00288mm²的小面积。

💡 主要创新点

• 提出延迟少电容反馈均衡器（CFE），实现低功耗PAM-4均衡。
• 单端PAM-4接收器设计，支持32Gb/s/pin高数据速率。
• 在28nm CMOS工艺下实现0.3pJ/b的超低能耗比。

🏷 关键词

📄 原文摘要

multi-level signaling techniques such as PAM3 and PAM4 are being increasingly adopted [1-7]. However, the lower SNR due to multi-level signaling necessitates complex equalization, increasing power consumption and area. This paper presents a delay-less capacitivefeedback equalizer (CFE) that performs low-power equalization for PAM4 signaling. The RX, fabricated in a 28nm CMOS technology, achieves an energy efficiency of 0.3pJ/b at 32Gb/s/pin and occupies an active area of 0.00288mm2. Figure 22.5.1 compares typical RX-equalization approaches. Decision-feedback equalizers (DFE) are commonly used due to their effectiveness in canceling post-cursor inter-symbol interference (ISI) without amplifying noise. However, the DFE is limited by timing closure

👥 作者与机构

Junseob So, Youngwook Kwon, Seungwoo Park, Seongcheol Kim,

Changmin Sim, Hwaseok Shin, Seon-Been Lee, Taehwan Kim, Chulwoo Kim Korea University, Seoul, Korea To meet increasing demands for higher throughput from memory interfaces,