⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一款基于16nm FinFET工艺的12GS/s 9位16倍时间交织SAR ADC，通过时间交织架构实现高速模数转换，解决了高速与高能效之间的平衡问题。
Michael Elliott4, Stuart McCracken1, Jack Kenney2, Janet Brunsilius3, Anil Korkmaz5, Enrique Alvarez Fontecilla3, Nevena Rakuljic3, Ushma Mehta3, Ben Sullivan1, Jeremy Scuteri5, Bac Binh Luu3, Mitchell Nichols3, Dara Martin6, Richard Sullivan5, Daniel DeBolt1, Ron Kapusta1 Analog Devices, Wilmington, MA Analog Devices, Somerset, NJ 3 Analog Devices, San Diego, CA 4 Analog Devices, Austin, TX 5 Analog Devices, Durham, NC 6 Analog Devices, Limerick, Ireland 1 2 Time-interleaved (TI) SAR ADC architecture is preferred in the low-to-moderate resolution space to achieve >GS/s speed for its excellent power and area efficiency [1-3], as well as to reduce design complexity, which may lead to fewer tape-outs and faster product development. High-speed and medium-resolution ADCs are used in applications like wireless communications and portable instrumentation. Emerging applications such as RF direct sampling in fully digital phased arrays require similarly high sample rates, but they
Junhua Shen1, Wei-Hung Chen2, Efram Burlingame3, Stephen Weinreich1,