A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology its leakage is eliminated and INCM returns to VDDA to stop P1 leakage. When opaque LCLKT is at VDDA and the cross-coupled NMOS/PMOS latch is enabled; input switching does not propagate to the output until the latch is transparent.

📋 论文概要

本文提出了一款采用3nm FinFET工艺的38Mb/mm²高密度双轨SRAM，工作电压为380/540mV。该设计通过消除泄漏电流和使INCM返回VDDA停止，实现了超低功耗和高密度。

💡 主要创新点

• 采用双轨供电（380/540mV）实现超低电压操作，同时保持高密度。
• 创新地消除了泄漏电流，并设计了INCM返回VDDA停止机制，进一步降低静态功耗。
• 基于3nm FinFET工艺，实现了38Mb/mm²的面积效率。

🏷 关键词

📄 原文摘要

Prasanna Nalawar4, Yogeshbhai Patel2, Shailendra Sharad2, Shakti Singh2 A clock buffer with high-voltage LS bypass is shown in Fig. 29.4.3, its design supports an extended voltage range when a large forward split is applied, but without the ERLS serial delay. The external VDD-driven clock, CLK switches the buffer to generate the internal SRAM clock, CLKIB. A parallel clock path in the VDDA domain, CLK_VDDA arrives after the ERLS delay; as the forward split increases, the CLK_VDDA path enables the complete transition of CLKIB to VSS. RSTB is an end-of-cycle reset. The delay vs. forward split simulation graph in Fig. 29.4.3 compares the original design, without the parallel CLK_VDDA, to this work for the worst-case slow-N/fast-P process corner. Clock buffer delays diverge after small forward split. The original design fails after a 600mV forward split, while the new design maintains a near-constant delay at a 800mV forward split.

👥 作者与机构

Harold Pilo1, John Barth1, Kapil Dev Dwivedi2, Peter Lee3, Vikram Kumar2,