An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration

📋 论文概要

该论文提出一种易于驱动的16MS/s流水线逐次逼近（pipelined-SAR）ADC，采用分裂粗-细输入缓冲器采样方案，有效降低了对输入驱动的要求；同时结合快速鲁棒背景校准技术，解决了传统架构中采样电容大、驱动困难以及残余放大器功耗高等问题。

💡 主要创新点

• 提出分裂粗-细输入缓冲器采样方案，降低了对输入驱动电源电压或预测器的依赖，拓宽了应用场景。
• 采用快速鲁棒背景校准技术，无需额外高功耗放大器即可实现高精度转换。
• 结合能量高效的流水线SAR架构与动态放大器，进一步优化了功耗与速度的权衡。

🏷 关键词

📄 原文摘要

realized utilizing the energy-efficient pipelined-SAR architecture [1-2]. However, a large sampling capacitance is required to suppress the thermal noise, making ADCs challenging to drive. Although the integrated driving techniques have been explored, they still require either a higher supply [3-6] or a predictor [7-8], limiting its application scenarios. Another factor that may limit the energy efficiency is the residue amplifier, which costs substantial power to achieve a sufficient bandwidth for settling. The use of an energy-efficient dynamic amplifier can address this problem [9-11], but it often suffers from inter-stage gain variation under PVT conditions, necessitating background calibration [12-17]. This calibration must be fast, robust and capable of working under different input conditions. This work presents

👥 作者与机构

Zhuoyi Chen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan,

Ru Huang, Linxiao Shen Peking University, Beijing, China High-resolution ADCs operating at medium speed (1-20MS/s) can be effectively