An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with

📋 论文概要

该论文提出了一种8位10GS/s的双通道时间交织流水线ADC，采用并发残差传输与量化技术以及自动缓冲器功率门控技术，解决了高速时域ADC对PVT变化敏感的问题，实现了高速高鲁棒性的模数转换。

💡 主要创新点

• 提出并发残差传输与量化技术，减少了流水线级间延迟，提高了转换速度。
• 实现自动缓冲器功率门控，根据工作状态动态调节功耗，降低了整体功耗。
• 采用双通道时间交织架构，结合电压域流水线ADC，实现了10GS/s的高采样率。

🏷 关键词

📄 原文摘要

Yunsong Tao, Mingtao Zhan, Mingyang Gu, Xiyu He, Yuxuan He, Zhishuai Zhang, Yi Zhong, Lu Jie, Nan Sun Tsinghua University, Beijing, China High-speed (~10GS/s) medium-resolution (~8b) ADCs are key blocks for wideband applications. Time-domain ADCs can achieve 5GS/s single-channel speed [1,2], but their reliance on matched gate delays leads to high sensitivity to PVT variations and device mismatches. By comparison, voltage-domain (flash/SAR/pipeline) ADCs are more robust against PVT and mismatches. However, flash ADCs are limited to 6b for their exponentially growing complexity with resolution [3]. SAR ADCs are efficient at 8b, but their limited single-channel speed (<1.5GS/s) necessitates a large number of time-interleaved (TI) channels [4], causing large implementation and calibration overhead. Pipelined ADCs are faster than SAR, but their speed is still limited to 3GS/s due to 3 basic operations in series

👥 作者与机构

Concurrent Residue Transfer and Quantization, and Automatic, Buffer Power Gating