A 14b 1GS/s Single-Channel Pipelined ADC with a Parallel-Operation SAR Sub-Quantizer and a DynamicDeadzone Ring Amplifier

📋 论文概要

本文提出一款14位1GS/s单通道流水线ADC，采用并行操作SAR子量化器和动态死区环形放大器，以降低功耗并改善PVT敏感性。通过创新电路结构解决了传统流水线ADC中功耗高和偏置调节复杂的问题。

💡 主要创新点

• 提出并行操作SAR子量化器替代传统多比特flash量化器，降低功耗和面积。
• 采用动态死区环形放大器，无需外部偏置调节，增强PVT鲁棒性。

🏷 关键词

📄 原文摘要

and high resolution (&14b) are required for wireless communication and instrumentation applications. The conventional pipelined architecture is usually power-hungry due to the substantial use of residue amplifiers (RAs) and flash quantizers. In [1], a low-power ring amplifier (ringamp) is exploited as the RA in a 15b 1GS/s pipelined ADC, achieving excellent power efficiency (<10fJ/conv.-step) and high SNDR (>67dB). However, the ringamp requires bias tuning to track PVT variations, and the five pipelined stages with multi-bit flash are still potential power bottlenecks. [2] adopts current biasing and split MDAC to improve the PVT robustness of the ringamp and utilizes a backend time-interleaved (TI) SAR to reduce the number of stages, and thereby

👥 作者与机构

Yue Cao1, Yi Shen1,2, Shubin Liu1,2, Haolin Han1, Hongzhi Liang1, Li Dang1,

Dengquan Li1, Ruixue Ding1,2, Zhangming Zhu1,2 Xidian University, Xi’an, China Hangzhou Institute of Technology, Xidian University, Hangzhou, China 1 2 Pipelined ADCs with high speed (&1GS/s)