⚡ 本页包含 AI 生成的分析内容，仅供参考
本文实现了一款1Tb容量、3比特每单元的3D闪存芯片，通过创新的读取操作技术将读取能效提升了29%，并采用电源隔离低抽头架构实现了4.8Gb/s的数据传输速率，旨在满足AI应用对高容量、高能效存储的需求。
Yumi Higashi1, Yutaka Shimizu1, Akihiro Imamoto1, Kazuaki Kawaguchi1, Koji Tabata1, Takeshi Nakano1, Yusuke Ochi1, Hiroaki Hoshino1, Takeshi Hioka1, Shigehito Saigusa1, Hiroki Date1, Masaki Unno1, Jumpei Sato1, You Kamata1, Hardwell Chibvongodze2, Naoki Ojima2, Hiroshi Sugawara2, Masahiro Kano2, Jang-woo Lee2, Hiroyuki Mizukoshi2, Ryuji Yamashita2, Kensaku Abe2, Naohito Morozumi2, In-Soo Yoon2, Takuya Ariki2, Jong Hak Yuh2, Khin Htoo2, Yosuke Kato2, Yoshihisa Watanabe1, Toshiyuki Kouchi1 KIOXIA, Tokyo, Japan Western Digital, Milpitas, CA 1 2 3D Flash memory [1-8] is expanding into AI applications, where high-speed I/O and high read performance is essential, particularly for big data applications [1,4]. It is critical for high-speed circuits to be small enough and to not overhang the memory array of a CMOS directly bonded to the array (CBA) [1,2] or CMOS under array (CUA) [3-8] due to the stacking nature of the CMOS circuits and memory array. Reducing circuit overhang, from
Kosuke Yanagidaira1, Mario Sako1, Yasuhiro Hirashima1, Junya Matsuno1,