A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW

📋 论文概要

本文提出了一种PVT鲁棒的2倍交错2.2GS/s ADC，采用基于门控环形振荡器的量化器并在通道和步骤间共享，实现了超过4.5G的性能。该设计解决了传统环形振荡器ADC在PVT变化下的性能退化问题，提升了能量和面积效率。

💡 主要创新点

• 提出门控环形振荡器(Gated-CCRO)作为量化器，通过通道和步骤共享降低功耗和面积。
• 采用2倍交错架构并实现PVT鲁棒性，在工艺、电压、温度变化下保持高性能。

🏷 关键词

📄 原文摘要

Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 The demand for medium-resolution GS/s ADCs is increasing in DSP-based wireline communication. Enhancing energy and area efficiency of the unit ADC is crucial for facilitating a higher data throughput with massive interleaving. Ring oscillator (RO)-based ADCs [1-4] are promising due to their compact and scaling-friendly nature, but they face challenges, as reviewed in Fig. 24.3.1. A voltage-controlled RO (VC-RO) with a counter [1] simplifies ADC conversion by directly converting the sampled input voltage into digital codes. However, the nonlinear tuning curve of VC-RO necessitates extra calibration. Additionally, since the sampled voltage directly modulates the frequency of VC-RO, each sub-channel ADC requires an individual VC-RO, which undermines efforts to minimize the overall energy and area. Gated RO (GRO)-based ADCs [2] have better energy efficiency by

👥 作者与机构

Junlin Zhong1, Minglei Zhang1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1

University of Macau, Macau, China