ISSCC 2025Session 4 · ANALOG TECHNIQUESAnalog Circuits

A 0.4µW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C of the capacitor charging, the relationship between the period with VOS and Td can be calculated. Compared with the conventional structure, the proposed one has significantly improved robustness, as shown in Fig. 4.5.1 (top right). The circuit implementation and timing diagram are detailed in Fig. 4.5.3. It is mainly

📄 原文摘要

Hongshuai Zhang1, Jiaxin Liu1, Zheng Wang1, Mingkang Zhang3, Na Yan4, Jun Yin2, counter, and the comparator. The dynamic switches in the VREF generator are triggered by the output signal Φ. When Φ=1, VREF is generated by the voltage division of the resistors R1 Pui-In Mak2, Shiheng Yang1 University of Electronic Science and Technology of China, Chengdu, China 2 University of Macau, Macau, China 3 M-CHIP, Chengdu, China 4 Fudan University, Shanghai, China 1 RC oscillators as timers have shown improved frequency stability in recent years [1-23]. However, controlling their robustness against PVT variations often incurs extra area and power budgets. The closed-loop RC oscillators ([4-13]), aided by a frequency-locked loop (FLL), can outperform their open-loop counterparts in terms of frequency stability, but at the expense of area, power and circuit complexity (e.g. switched resistors [8-12] and

👥 作者与机构

Yueduo Liu1, Zihao Zhu1, Xinyu Yang1, Rongxin Bao1, Zehao Zhang2, composed of a VREF generator, an RC branch, a pulse generator, REF replication, a 1bit

分类：Analog Circuits · 年份：ISSCC 2025