A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension

📋 论文概要

本文提出一种28nm CMOS 500MS/s 12b三阶段流水线SAR ADC，采用三级级联单级浮动残差放大器与虚拟电源扩展技术，提高了效率和线性度。该ADC在240MHz输入下达到63.4dB SNDR和81.0dB SFDR，功耗6.64mW，面积0.011mm²。

💡 主要创新点

• 提出三级级联单级浮动残差放大器（triple-cascode FIA）结构，用于流水线SAR ADC的级间残差放大。
• 采用虚拟电源扩展技术，在不增加额外电源电压的情况下提升放大器线性度和效率。
• 集成片上数字校准，补偿PVT变化和电路非理想性。

🏷 关键词

📄 原文摘要

(ECAs) 1 Abstract This paper presents a 28nm CMOS 500MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4dB SNDR and 81.0dB SFDR at 240MHz input across PVT variations, consuming 6.64mW with on-chip digital calibrations and occupying 0.011mm2. Over the past decade, the pipeline-SAR converter has emerged as a hybrid architecture in which each stage is implemented as a SAR ADC. In this context, interstage residue amplifiers (RAs) play a crucial role, as they must meet stringent speed, linearity, and noise requirements. Their design is challenging, and they can account for up to 40% of the overall

👥 作者与机构

Michele Rocco*1, Gabriele Zanoletti*1, Alessia Ceroni*1, Giacomo Tombolan1, Gabriele Bè1,2, Luca Ricci1, Salvatore Levantino1, Andrea Leonardo Lacaita1,

Luca Bertulessi1, Carlo Samori1, Andrea Giovanni Bonfanti1 Politecnico di Milano, Milan, Italy, 2now with Infineon Technologies, Villach, Austria *Equally Credited Authors