A 13b 500MS/s 94dB-SFDR Resistive-Input Pipelined-SAR ADC with Linear and Efficient Current-Buffer-Based Integrating Sampler

📋 论文概要

本文提出了一种流水线SAR ADC，采用基于电流缓冲器的积分采样器实现电阻输入和高线性度；通过浮空电荷转移器与多比特预转换技术实现线性残差放大并加速第二级转换。该ADC在250MHz奈奎斯特输入下实现了94.5dB SFDR，为200MS/s以上离散时间ADC中最高。

💡 主要创新点

• 提出基于电流缓冲器的积分采样器，实现电阻输入并保持高线性度。
• 提出浮空电荷转移器(FCT)结合多比特预转换(MB-PC)，实现线性残差放大并加速第二级转换。

🏷 关键词

📄 原文摘要

Abstract This work proposes a pipelined-SAR ADC featuring a current-buffer-based integrating sampler that presents a resistive input with good linearity. A floating charge transferrer (FCT) with multi-bit pre-conversion (MB-PC) enables linear residue amplification and accelerates the second-stage conversion. The prototype ADC achieves an SNDR of 67.5dB and an SFDR of 94.5dB under a Nyquist input at 250MHz. This SFDR is the highest reported for discrete-time ADCs operating above 200MS/s. Wideband ADCs have advanced significantly at both the architecture and circuit levels. As the performance and energy efficiency of ADC cores continue to improve, the frontend often emerges as the system bottleneck. Figure 11.4.1 summarizes the representative ADC frontend structures. Conventional Nyquist ADCs with switched-capacitor (SC) sampling frontends impose a large capacitive load that necessitates a power-hungry input buffer [13]. Additional filters are also indispensable to address aliasing, incu

👥 作者与机构

Xiyu He, Mingyang Gu, Yunsong Tao, Siyu Huang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Tsinghua University, Beijing, China