A PVT-Robust Frequency-Scalable Fully Dynamic ΔΣ ADC with Bottom-Plate Level Shift

📋 论文概要

本文提出一种全动态、免校准的ΔΣ ADC，采用底板电平移位（BPLS）技术实现电容退化积分器，通过采样负电荷降低阈值电压依赖性、改善建立时间并消除kT/C噪声，仅用0.5pF采样电容。该ADC在10kHz带宽下达到91.7dB峰值SNDR和95.6dB动态范围，功耗10.1mW，且在±10%电源电压或-40至100°C范围内性能退化小于2dB，实现了PVT鲁棒性和频率可扩展性。

💡 主要创新点

• 提出底板电平移位（BPLS）技术，通过采样负电荷补偿阈值电压变化，同时改善积分器建立并消除kT/C噪声，从而允许使用极小采样电容（0.5pF）。
• 实现全动态、无校准的ΔΣ调制结构，在PVT变化下保持高动态范围（DR>184dB），且带宽可在1-40kHz范围内灵活扩展。

🏷 关键词

📄 原文摘要

Abstract A fully dynamic calibration-free ΔΣ ADC using capacitive-degeneration integrators with bottom-plate level shift (BPLS) is presented. BPLS samples negative charge to reduce threshold-voltage dependence, improve settling, and cancel kT/C noise, enabling 0.5pF sampling capacitance. The ADC achieves 91.7dB peak SNDR and 95.6dB DR with 10.1mW at 10kHz bandwidth (BW). Up to 40kHz BW, the worst-case DR degradation is %2dB under ±10%VDD or -40 to 100°C. FoMS,DR is 185.6dB (10kHz BW) and >184dB (1-to-40kHz BW). High-dynamic-range, frequency-scalable ADCs are useful across many sensing tasks and can reduce development costs. Noise-shaping architectures employing dynamic integrators are attractive for energy-efficient conversion and frequency scalability. The left side of Fig. 32.2.1 shows three established implementations. Passive integrators [1-3] are powerefficient, but their low loop gain makes it difficult to achieve high SQNR. Closed-loop

👥 作者与机构

Tohru Kaneko1, Hideaki Ishida1, Yuzuru Yamaki1, Satoshi Takehara1, Un-Ku Moon2

Asahi Kasei Microdevices, Yokohama, Japan, 2Oregon State University, Corvallis, OR