An 8b 20GS/s Time-Interleaved ADC with 2.6mW 1GS/s Hybrid Voltage/Time-Domain Sub-ADC in 12nm FinFET

📋 论文概要

本文提出了一款2.6mW、1GHz、42dB-SNDR的混合电压/时间域子ADC，通过避免传统SAR比较器的折衷并利用时间域ADC的能效优势，实现了低功耗高性能。同时引入分层采样保持电路和新型共模反馈方案，增强了信号分配，并最终实现了20GHz时间交织ADC。

💡 主要创新点

• 采用混合电压/时间域架构，避免了传统SAR ADC中比较器的速度与精度折衷，提升了能效。
• 提出分层采样保持电路与新型共模反馈方案，改善了高频信号分配性能。

🏷 关键词

📄 原文摘要

Satoshi Yoshizawa, Atsuya Suzuki, Soichi Kato, Takahiro Naito, Keigo Bunsen, Tomohiro Matsumoto, Yasushi Katayama Sony Semiconductor Solutions, Atsugi, Japan Abstract A 2.6mW, 1GHz, 42dB-SNDR sub-ADC is presented. A hybrid voltage- and time-domain architecture is employed to avoid the theorical SAR comparator trade-offs and enable power efficiency benefit from the time-domain ADC. Additionally, a hierarchical sample-and-hold circuit with a new common-mode feedback scheme is introduced to enhance signal distribution. A 20GHz time-interleaved ADC, including an input buffer and reference, demonstrates an SNDR of 37dB with a power consumption of 135mW. High-speed DSP-based wireline transceivers require medium-resolution (6-8b) ADCs that operate at multi-GHz sampling rates while maintaining low power consumption. SAR ADCs are a preferred choice due to their high energy efficiency and robustness for sub-channels

👥 作者与机构

Daisuke Miyazaki, Yuki Yagishita, Mika Takasaki, Shun Nagata, Takeru Nogamida, Yudai Abe, Kazutoshi Tomita, Kazunori Hasebe, Toshiyuki Kikkawa,