A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers

📋 论文概要

本文提出一种紧凑型7位175GS/s时间交织斜率ADC，采用开关输入缓冲器实现宽带采样，并通过非线性斜率补偿分层采样网络的静态非线性。该ADC在5nm CMOS中面积仅0.063mm²，能效低于2.16pJ/样点，适用于100Gb/s/lane以上的有线通信标准。

💡 主要创新点

• 提出开关输入缓冲器结构，实现宽带采样并驱动时间交织采样器。
• 利用非线性斜率补偿分层采样网络的静态非线性，提升线性度。
• 采用带前馈耦合的延迟线生成多相时钟，支持高速时间交织操作。

🏷 关键词

📄 原文摘要

conversion. Samplers with switched buffers are proposed to realize wideband sampling in rank 1 driven by a multi-phase clock generated by a delay line with feedforward coupling. Making the slope nonlinear compensates static nonlinearities of the hierarchical sampling network. With only 0.063mm2 in 5nm CMOS, it is the smallest ultra-high-speed ADC reported to date with an excellent energy per sample of less than 2.16pJ. Recent wireline communication standards like IEEE 802.3db/df/dj increase bit rates to 100Gb/s/lane and beyond. An analog-to-digital converter (ADC) based receiver (RX) offers powerful digital processing to correct imperfections, which benefits from technology scaling in terms of power and area [1]. Realizing ADC-based receivers at these high speeds require

👥 作者与机构

Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Renukaswamy, Lucas Moura Santana,

Jorge Lagos Benites, Nereo Markulić, Jan Craninckx imec, Leuven, Belgium Abstract We present a 2048× time-interleaved slope-ADC implementing 7b, 175GS/s