An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization

📋 论文概要

本文提出了一种具有双残差架构的增量流水线ADC，通过指数ΔΣ环路直接量化残差，取代了传统复杂且精度较低的插值器，实现了快速高精度的后端转换，同时保持对级间增益变化的不敏感性。原型芯片达到了85.1dB SNDR和8MS/s转换速度，在同类双残差ADC中SNDR最高，在同类高精度增量ADC中速度最快。

💡 主要创新点

• 提出双残差辅助的指数量化架构，用指数ΔΣ环路直接量化残差，替代传统插值器，提高了精度和速度。
• 该架构对级间增益变化不敏感，增强了鲁棒性，简化了设计复杂度。

🏷 关键词

📄 原文摘要

Abstract This paper presents an incremental pipeline ADC with dual-residue architecture. An exponential ΔΣ loop is proposed to directly quantize the residue, replacing conventional interpolators that are complex and less accurate. It enables fast and high-precision backend conversion while maintaining insensitivity to inter-stage gain variations. The prototype achieves 85.1dB SNDR, the highest among comparable dual-residue ADCs, and 8MS/s conversion speed, the fastest among comparable high-precision incremental ADCs. Incremental ADCs are gaining increasing attention for their high resolution, low latency, and easy system multiplexing [1]–[6]. Recent developments have leveraged pipelined incremental architectures for a better balance between power efficiency and conversion speed [7], [8]. However, ensuring accurate residue amplifier (RA) gain remains a critical challenge in high-resolution pipelined designs. Closed-loop amplifiers offer precise interstage gain but often incur high power

👥 作者与机构

Zongnan Wang, Bingrui Li, Haoyang Luo, Chenyuan Chu, Jiachang Yang, Yuan Wang, Xiyuan Tang

Peking University, Beijing, China