A 28nm CMOS SAR-Based Continuous-Time Pipeline ADC with 103dB SFDR and 270MHz Bandwidth Using NCF and DAC Error Calibration

📋 论文概要

这篇论文提出了一种基于SAR的连续时间流水线ADC，采用噪声消除滤波器和DAC误差校准技术，在28nm CMOS工艺下实现了103dB SFDR和270MHz带宽，功耗155mW，面积1.4mm²，适用于汽车雷达和高端信息娱乐系统。

💡 主要创新点

• 提出高线性度全通滤波器实现宽带高频谱纯度。
• 采用快速音调频域噪声消除滤波器校准和基于相关的逐元素DAC增益与时序误差校准。

🏷 关键词

📄 原文摘要

receivers achieves -95dBc THD and 103dB SFDR in 270MHz bandwidth, exceeding state-of-the-art by >20dB. Wideband high spectral purity is realized with a highly linear all-pass filter, high- SFDR coarse ADCs, a fast tone-based frequency-domain noise-cancellation filter calibration and a correlation-based element-wise DAC gain and timing error calibration. Power and area, including LDOs and calibrated filters is 155mW and 1.4mm2. Automotive grade receivers for FMCW radar sensors and high-end car infotainment systems require ADCs with very high linearity (-100dB THD) and spectral purity (>100dB SFDR). A continuous-time (CT) delta-sigma (DS) modulator is the preferred architecture as it combines inherent anti-alias filtering, easy drivability, high dynamic range and superb

👥 作者与机构

Qilong Liu1, Robert Rutten1, Muhammed Bolatkale1, Arda Aralioglu1, Gilbert Hardeman1, Emil Siby1, Patrick van Mourik1, Vinoth Ilamurugan2, Shagun Bajoria1, Lucien Breems1

NXP Semiconductors, Eindhoven, The Netherlands, 2NXP Semiconductors, Delft, The Netherlands 1 Abstract This 28nm CMOS SAR-based continuous-time pipeline ADC for automotive