A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration

📋 论文概要

本文提出一款14位400MS/s的TDC辅助流水线逐次逼近型ADC，采用线性化轨到轨输入电压-时间转换器（VTC）。通过背景校准引擎校正VTC增益和时域偏移误差，并利用复制偏置环形放大器提升能效和鲁棒性。在28nm工艺下实现了67dB奈奎斯特SNDR、4.6mW功耗，FoMw为6.3fJ/conv-step，FoMs为173.5dB。

💡 主要创新点

• 提出前端TDC配合线性化轨到轨输入VTC，实现宽输入摆幅下的高线性度时间域量化。
• 开发背景校准引擎，通过监测数字输出统计量校正VTC增益和时域偏移误差，模拟开销小。
• 采用复制偏置环形放大器，提升环放输出摆幅和能量效率，增强工艺鲁棒性。

🏷 关键词

📄 原文摘要

Abstract This paper presents a 14b 400MS/s Pipelined-SAR ADC utilizing a front-end TDC with a linearized rail-to-rail input VTC. A background calibration engine corrects VTC gain and timedomain offset errors by monitoring digital output statistics with minimal analog overhead. A replica-biasing-based ring amplifier improves energy efficiency and robustness. The 28nm chip achieves 67dB Nyquist SNDR at 4.6mW with a 6.3fJ/conv-step FoMw and 173.5dB FoMs. The proliferation of 5G/6G communications and high-speed wireline systems creates a relentless demand for ADCs achieving both high resolution (≥14b) and sampling rates well into the hundreds of MS/s. The pipelined-SAR architecture has become a popular solution, effectively balancing power efficiency with the required conversion speed. However, the sequential bit-cycling of the frontend SAR often becomes the primary speed bottleneck. To break this latency barrier, the time-domain (TD) quantizer, which employs a voltage-to-time

👥 作者与机构

Jingpeng Wang1, Bingrui Li1, Haoyang Luo1, Mingtao Zhan2, Xiyu He2, Dawei Shen1, Lu Jie2, Xiyuan Tang1

Peking University, Beijing, China, 2Tsinghua University, Beijing, China