Data Converters — ISSCC 知识库

ISSCC 2023 Session 10 Data Converters

A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations

Sung-En Hsieh, Tzu-Chien Wu, Chun-Chih Hou

Direct RF sampling reduces complexity for receiver design. However, SNDR and speed specifications of its ADCs are stringent, which makes the time-interleaved (TI) ADC attractive for the required sampling rate. There is a

MediaTek, Hsinchu, Taiwan

ISSCC 2022 Session 25 Data Converters

An 84dB-SNDR Low-OSR 4th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique

Tzuhan Wang*, Tian Xie*, Zhe Liu, Shaolan Li

*Equally Credited Authors (ECAs) With the combined merits of SAR and ∆Σ ADCs, the noise-shaping (NS) SAR architecture can achieve high resolution with a mild OSR, making it versatile for a wide range of applications. Non

Georgia Institute of Technology, Atlanta, GA

ISSCC 2022 Session 25 Data Converters

A 28nm 6GHz 2b Continuous-Time ∆Σ ADC with -101dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction

Muhammed Bolatkale1, Robert Rutten1, Hans Brekelmans1, Shagun Bajoria1,

continuous-time ∆Σ modulators with a (theoretically) linear 1b DAC, have demonstrated better than -100dBc THD in a bandwidth range from tens of kHz for audio to tens of MHz for broadband AM/FM radio [1]. To achieve both

Yihan Gao1, Bernard Burdiek2, Lucien Breems1 NXP Semiconductors, Eindh

ISSCC 2022 Session 25 Data Converters

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ∆Σ ADC in 40nm CMOS

Qilong Liu1,2, Lucien Breems1,2, Chenming Zhang1,2, Shagun Bajoria1,2,

University of Technology, Delft, The Netherlands 1 2 In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hu

Muhammed Bolatkale2,3, Robert Rutten2, Georgi Radulov1 Eindhoven Unive

ISSCC 2022 Session 25 Data Converters

A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS

Calvin Yoji Lee, Un-Ku Moon

Demands for battery-powered consumer electronics have driven the evolution of powerefficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery

Oregon State University, Corvallis, OR

ISSCC 2022 Session 25 Data Converters

A 2.87µW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC using FIA with Dynamic-Body-Biasing Assisted CLS Technique

Yaopeng Hu1, Yibo Zhao1, Wanyuan Qu1, Le Ye2, Menglian Zhao1, Zhichao Tan1

Peking University, Beijing, China 1 2 Micro-power ∆Σ modulators are suitable for low-bandwidth, high-precision applications, such as smart sensors, biomedical signal processing and battery-powered IoT devices. They achie

Zhejiang University, Hangzhou, China

ISSCC 2022 Session 25 Data Converters

A 4.4µW 2.5kHz-BW 92.1dB-SNDR 3rd-Order VCO-Based ADC with Pseudo Virtual Ground Feedforward Linearization

Corentin Pochet, Drew A. Hall

The rise of the internet-of-things and distributed sensor nodes with machine-learning and edge processing are driving the need for low-power, high-precision ADCs. These highly digital systems are best implemented in adva

University of California, San Diego, CA

ISSCC 2022 Session 10 Data Converters

A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR

Lu Jie1, Mingtao Zhan1, Xiyuan Tang2, Nan Sun1

Peking University, Beijing, China 1 2 High-resolution (>100dB SNDR), kHz-BW ADCs are required by emerging IoT and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of int

Tsinghua University, Beijing, China

ISSCC 2022 Session 10 Data Converters

A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC

Yuyan Liu1, Menglian Zhao1, Yibo Zhao1, Xiaopeng Yu1, Nianxiong Nick Tan1,

applications, such as smart sensors and event-driven IoT devices, which need ADCs with high resolution, high power efficiency, and can be multiplexed between multiple inputs. Despite these advantages, they usually need a

Le Ye2, Zhichao Tan1 Zhejiang University, Hangzhou, China Peking Unive

ISSCC 2022 Session 10 Data Converters

A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS

Jesper Steensgaard1, Richard Reay2, Raymond Perry2, Dave Thomas2,

for low-to-medium speed applications. The ADC function accommodates a wide range of use, including Nyquistrate data acquisition and oversampled signal applications. The noise spectral density (NSD) is uniform from 0Hz to

Geoffrey Tu2, George Reitsma2 Analog Devices, Sequim, WA Analog Device

ISSCC 2022 Session 10 Data Converters

A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

Haoyi Zhao, Fa Foster Dai

The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requ

Auburn University, Auburn, AL

ISSCC 2022 Session 10 Data Converters

A 0.004mm2 200MS/s Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp

Mingtao Zhan1, Lu Jie1, Xiyuan Tang2, Nan Sun1

Peking University, Beijing, China 1 2 Pipelined ADCs are widely used for high-speed high-resolution applications, but there are two challenges. First, limited by the kT/C noise requirement, its 1st-stage sampling capacit

Tsinghua University, Beijing, China

ISSCC 2022 Session 10 Data Converters

A 0.82mW 14b 130MS/s Pipelined-SAR ADC with a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend

Jia-Ching Wang, Tai-Haur Kuo

To fulfill upcoming communication specifications, it has become popular recently to employ pipelined-SAR architectures, incorporating residue amplifiers (RA) to achieve high resolution, wide bandwidth, and low-power ADCs

National Cheng Kung University, Tainan, Taiwan

ISSCC 2022 Session 10 Data Converters

A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen

High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-do

University of Southern California, Los Angeles, CA

ISSCC 2021 Session 27 Data Converters

A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR Figure 27.7.3 shows the NS-SAR schematic and timing diagram. The LPF tracking and the SAR conversion take up 1/8 and 3/8 of a clock period, respectively. The rest is allocated for the residue amplification and integration.

Linxiao Shen1,2, Zijie Gao3, Xiangxing Yang2, Wei Shi2, Nan Sun2,3

For simplicity of design, this work uses top-plate sampling. To improve its linearity, 2 switches are used to disconnect CDAC from the nonlinear input capacitance of the comparator and the dynamic amplifier (DA) during t

ISSCC 2021 Session 27 Data Converters

A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration

Hongshuai Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2

Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 To suppress the gain error from dynamic-power amplifiers, recently presented approaches including gain-error shaping (GES) [1], digital amplifiers [2]

University of Macau, Macau, China

ISSCC 2021 Session 27 Data Converters

An 80MHz-BW 640MS/s Time-Interleaved Passive NoiseShaping SAR ADC in 22nm FDSOI Process

Chin-Yu Lin*, Ying-Zu Lin*, Chih-Hou Tsai, Chao-Hsin Lu

*Equally-Credited Authors (ECAs) Recently, both the number of smart devices and the amount of data transfered to and from these devices have grown at unprecedented rates. To provide users with a highquality experience, w

MediaTek, Hsinchu, Taiwan

ISSCC 2021 Session 27 Data Converters

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

Xiyuan Tang1, Xiangxing Yang1, Jiaxin Liu2, Wei Shi1, David Z. Pan1, Nan Sun1,2

Tsinghua University, Beijing, China 1 2 Many applications, such as multi-standard wireless and event-driven IoT devices, demand high-resolution ADCs with scalable sampling rate and power consumption. The conventional pip

University of Texas, Austin, TX

ISSCC 2021 Session 27 Data Converters

A 13.8-ENOB 0.4pF-CIN 3rd-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation

Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li

Noise-shaping SAR (NS-SAR) ADCs are attracting rising attention for their low-power high-resolution capability. In most recent arts, a substantial focus is placed on improving the loop filter design by using techniques s

Georgia Institute of Technology, Atlanta, GA

ISSCC 2021 Session 27 Data Converters

-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC

Kyojin Choo, Hyochan An, Dennis Sylvester, David Blaauw

IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to

University of Michigan, Ann Arbor, MI

ISSCC 2021 Session 27 Data Converters

A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering

Jiaxin Liu1, Dengquan Li2, Yi Zhong1, Xiyuan Tang3, Nan Sun1,3

Xidian University, Xi’an, China 3 University of Texas, Austin, TX 1 2 The noise-shaping (NS) SAR is an emerging hybrid architecture that aims to combine the benefits of both SAR and ∆Σ ADCs [1-8]. The key in an NS SAR is

Tsinghua University, Beijing, China

ISSCC 2021 Session 10 Data Converters

A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters

Martin Clara*1, Daniel Gruber*2, Albert Molina3, Matteo Camponeschi2,

Yu-shan Wang4, Christian Lindholm2, Hundo Shin5, Ramon Sanchez3, Christoph Duller2, Patrick Torta2, Kamran Azadet1 Intel, Santa Clara, CA Intel, Villach, Austria 3 Intel, Madrid, Spain 4 Intel, Hillsboro, OR 5 now with A

ISSCC 2021 Session 10 Data Converters

A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET

Daniel Gruber*1, Martin Clara*2, Ramon Sanchez3, Yu-shan Wang4,

*Equally-Credited Authors (ECAs) Future multi-band software-defined-radio base-stations for digital beamforming and massive MIMO applications depend heavily on the availability of highly linear and compact data converter

Christoph Duller1, Gerald Rauter1, Patrick Torta1, Kamran Azadet2 Inte

ISSCC 2021 Session 10 Data Converters

A 12b 600MS/s Pipelined SAR and 2×-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET chip-to chip gain variation of the residue signal path. Moreover, the area-consuming 7b CDAC can be used in calibrating inter-stage offset error by adding offset in the feedback signal. Therefore, the comparator without offset calibration enables the SAR to enhance conversion speed.

Seungyeob Baek, Ilhoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim,

Youngjae Cho, Jongshin Shin Figure 10.5.3 shows the proposed adaptive speed-controlled (ASC) clock generation scheme. The ASC clock generator takes advantages from both the synchronous and asynchronous schemes by generat

ISSCC 2021 Session 10 Data Converters

A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR

Wei Shi1, Jiaxin Liu2, Abhishek Mukherjee1, Xiangxing Yang1, Xiyuan Tang1,

design suffers from a few challenges. First, it requires a large number of OTAs [1]. This increases the design complexity and power. In addition, each OTA contributes extra phase delay, whose reduction requires increasin

Linxiao Shen1, Wenda Zhao1, Nan Sun1,2 University of Texas, Austin, TX

ISSCC 2021 Session 10 Data Converters

A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer

Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn

Emerging communication and radar applications place enormous demands on ADC performance by requiring wide BW (100MHz) and high DR (70dB). Continuous-time delta-sigma modulators (CT-DSM) [1-2] are a mainstream solution as

University of Michigan, Ann Arbor, MI

ISSCC 2021 Session 10 Data Converters

A 139µW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs comparator non-idealities (e.g., signal-dependent delay) degrade the SQNR mostly in the main feedback path and not the auxiliary path. No extra fast path DAC or summing network is needed.

Somok Mondal1,2, Omid Ghadami1, Drew A. Hall1

The first integrator, shown in Fig. 10.2.3, is realized by a 4-stage amplifier with feedforward compensation. Two versions of the OTA, a 1- and 3-stack, were designed for comparison. For the tailless 3-stack version, the

ISSCC 2021 Session 10 Data Converters

A 116µW 104.4dB-DR 100.6dB-SNDR CT ΔΣ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter

Chilun Lo, Jongmi Lee, Yong Lim, Younghyun Yoon, Hyunseok Hwang,

applications because of its high energy efficiency and driving-friendly front-end compared with its discrete time counterpart. A resistive DAC (R-DAC) is widely used for its intrinsic low flicker noise. However, the desi

Jaehoon Lee, MooYeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee Sam