A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

📋 论文概要

该论文提出了一种0.97mW、260MS/s、12位流水线SAR ADC，采用基于环形TDC的细量化器实现PVT鲁棒的自动跨域缩放。解决了传统残差放大器功耗大、线性度要求高和PVT敏感的问题。

💡 主要创新点

• 使用环形TDC代替传统电压域细量化器，实现跨域缩放，降低功耗并提高PVT鲁棒性。
• 提出自动跨域缩放技术，无需额外校准即可适应PVT变化。

🏷 关键词

📄 原文摘要

The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requirement in subsequent stages. However, these amplifiers generally induce issues such as large power consumption, stringent linearity requirements, and PVT-sensitive gain errors [1,4]. Moreover, reduced voltage dynamic range in deep submicron nodes presents challenges for the design of high-performance amplifiers and fine quantizers in voltage domain. Therefore, implementing the fine quantizer in time domain becomes attractive due to its better noise tolerance and lower power consumption. Nevertheless, the linearity and conversion speed of the time-todigital converter (TDC) used as the fine quantizer degrades quickly with the increase of its resolution due to the exponentially increased hardware. Moreover, its full-scale and

👥 作者与机构

Haoyi Zhao, Fa Foster Dai

Auburn University, Auburn, AL