A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS

📋 论文概要

本文提出了一款24位2MS/s的SAR ADC，采用180nm CMOS工艺，实现了0.03ppm的积分非线性（INL）和106.3dB的动态范围（DR），解决了低至中速高精度数据采集应用的需求。该ADC具有均匀的噪声谱密度，适用于Nyquist-rate和过采样信号处理。

💡 主要创新点

• 实现了24位精度下极低的0.03ppm INL，突破传统SAR ADC的非线性限制。
• 通过均匀噪声谱密度设计，使品质因数FoM独立于所选带宽，适用于多种应用场景。
• 基于SAR架构在180nm工艺下同时实现高分辨率、高动态范围和2MS/s采样率，平衡了性能与功耗。

🏷 关键词

📄 原文摘要

for low-to-medium speed applications. The ADC function accommodates a wide range of use, including Nyquistrate data acquisition and oversampled signal applications. The noise spectral density (NSD) is uniform from 0Hz to Fs/2=1MHz, and hence FoM1 = DR + 10·log(BW/Power) is the same for any BW selected by decimation filtering or other DSP. The SNDR is within 1dB of the DR for full-scale input tones at frequencies up to 100kHz, and hence FoM2 = SNDR + 10·log(BW/Power) is similar to FoM1 for the primary use cases. We use a SAR-type architecture to provide generic precision ADC functionality: Nyquist capable, optional oversampling, one sample at a time, power-down between conversions, no cycle latency, no common-mode requirement. Zero-order mismatch-shaping makes

👥 作者与机构

Jesper Steensgaard1, Richard Reay2, Raymond Perry2, Dave Thomas2,

Geoffrey Tu2, George Reitsma2 Analog Devices, Sequim, WA Analog Devices, Santa Clara, CA 1 2 This work aims at optimizing accuracy, noise, and power