University of Technology, Delft, The Netherlands 1 2 In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1-3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to layout parasitics due to the high sampling rates, and most important of all, are power hungry, consuming several hundreds of mW. In this paper, we propose a filtering multi-stage noise-shaping (MASH) ∆Σ ADC architecture that overcomes the abovementioned drawbacks. Passive delay compensating filters [4] are used to realize broadband and
Qilong Liu1,2, Lucien Breems1,2, Chenming Zhang1,2, Shagun Bajoria1,2,
Muhammed Bolatkale2,3, Robert Rutten2, Georgi Radulov1 Eindhoven University of Technology, Eindhoven, The Netherlands NXP Semiconductors, Eindhoven, The Netherlands 3 Delft