A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS

📋 论文概要

本文提出了一种采用单端环形放大器积分器的单环ΔΣ调制音频ADC，在180nm工艺下实现了0.0375mm²的小面积和203.5µW的低功耗，动态范围达到108.8dB。通过伪伪差分架构有效消除了闪烁噪声，适用于电池供电的消费电子设备。

💡 主要创新点

• 首次在单环ΔΣ调制器中采用单端环形放大器积分器，在保持高能效的同时显著减小芯片面积。
• 利用伪伪差分（PPD）架构实现闪烁噪声消除，无需传统斩波稳定技术，简化了电路设计。

🏷 关键词

📄 原文摘要

Demands for battery-powered consumer electronics have driven the evolution of powerefficient high-resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to increasing battery life and shrinking form-factors. Flicker noise poses an issue for such systems although the use of well-known techniques in state-of-the-art designs such as chopper stabilization [1-2] are often sufficient for its mitigation. Alternatively, the pseudo-pseudo-differential (PPD) architecture [3] has demonstrated flicker cancellation through the use of single-ended circuits although area and power savings promised by this technique remain undemonstrated. This paper presents a DT single-loop DSM audio ADC utilizing a single-ended ring-amplifier-based integrator to achieve 108.8dB DR with 203.5µW power consumption within a compact area of 0.0375mm2. The use of the PPD architecture with a merged adder contribute to

👥 作者与机构

Calvin Yoji Lee, Un-Ku Moon

Oregon State University, Corvallis, OR