A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR

📋 论文概要

本文提出一种Zoom-增量计数混合型ADC，在0.014mm²的小面积内实现了103dB SNDR和100dB全摆幅共模抑制比，解决了传统高分辨率ADC面积过大的问题，适用于IoT和智能传感应用。

💡 主要创新点

• 提出Zoom-增量计数混合架构，结合Zoom ADC的高分辨率优势和增量计数ADC的小面积优势。
• 通过创新电路设计实现103dB SNDR的同时将面积缩小至0.014mm²，并达到100dB全摆幅CMRR。

🏷 关键词

📄 原文摘要

Peking University, Beijing, China 1 2 High-resolution (>100dB SNDR), kHz-BW ADCs are required by emerging IoT and smart sensing applications. These ADCs are desired for their high efficiency, but low cost and ease of integration are also required, especially to be compatible with the advanced CMOS processes that the IoT processor prefers. The state-of-the-art solutions in this scenario, such as the zoom ADC [1], the DT or CT-DSM [2-3], and the SAR ADC [4] and its noiseshaping variants [5], have already achieved great energy efficiency with >180dB FOMs. However, most of them are large in area, and rely heavily on the analog performance of old CMOS technologies with high supply voltages. In this work, we propose a new architecture that combines the counting ADC and CT-incremental-DSM (CT-IDSM) in a zoom ADC framework. The proposed architecture is not only power efficient, but also compact in area, highly digital, and friendly to process down-scaling. It operates at

👥 作者与机构

Lu Jie1, Mingtao Zhan1, Xiyuan Tang2, Nan Sun1

Tsinghua University, Beijing, China