A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology

📋 论文概要

本文提出了一种在14nm工艺下实现的8位10GS/s两步时域ADC，通过延迟跟踪流水线SAR TDC技术实现了500fs的时间步长，解决了高速应用中传统电压域时间交织SAR ADC面积和功耗效率低的问题。

💡 主要创新点

• 采用延迟跟踪流水线SAR TDC结构，实现两步时域量化，有效降低了时间步长至500fs。
• 通过两步时域转换替代传统电压域时间交织，显著减小了芯片面积（2850μm²）和功耗（25fJ/转换步）。

🏷 关键词

📄 原文摘要

High-speed (>GS/s) medium-resolution ADCs are in high demand for wideband communication ICs. Meanwhile, the increasing cost in advanced technology nodes favors area-efficient ADC architectures. The traditional voltage-domain time-interleaved (TI) SAR ADC [1-2] is a popular choice for its superior power efficiency. However, its singlechannel sample rate is generally limited to <1GS/s, necessitating a large number of TI channels in high-sample-rate scenarios. It inevitably increases implementation overhead, including capacitive loading to the input driver and total area consumption. Recently, time-domain ADCs [3-5] have shown promising sampling speed, but are mostly based on thermometer coded time-to-digital converters (TDC). Unfortunately, the circuit complexity for such Flash TDC grows exponentially with the target bit resolution. Existing SAR TDCs [6] demonstrate a lower complexity but are generally limited in sample rate

👥 作者与机构

Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen

University of Southern California, Los Angeles, CA