技术领域

Data Converters

279 篇相关论文 (2008–2026)

ISSCC 2019 Session 20 Data Converters
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ
Wei Wang1, Chi-Hang Chan1, Yan Zhu1, Rui P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Driven by great demands for high data transfer rates in mobile communications, ADCs require wide bandwidths with low noise density and power consumpti
University of Macau, Macau, China
ISSCC 2019 Session 20 Data Converters
An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications
Chi-Yun Wang, Jen-Huan Tsai, Sheng-Yuan Su, Jen-Che Tsai,
rate, which speeds up the development of the next-generation wireless-LAN (WLAN) standard. To improve spectrum efficiency and serve more users in crowded areas while increasing maximum throughput, 802.11ax supports 1024QA
Jhy-Rong Chen, Chih-Hong Lou MediaTek, Hsinchu, Taiwan The demand for
ISSCC 2019 Session 20 Data Converters
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-CouplingAssisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS
Liang Qi1, Ankesh Jain2, Dongyang Jiang1, Sai-Weng Sin1,
Rui P. Martins1,3, Maurits Ortmanns2 University of Macau, Macau, China, University of Ulm, Ulm, Germany 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 The demands for wider cellular bandwidth (BW
ISSCC 2019 Session 20 Data Converters
An 8×-OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT ΔΣ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS
Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Ting-Yang Wang,
block in a cellular receiver design. A continuous-time delta-sigma modulator (CTDSM), which gets the benefit of inherent anti-alias filtering, is a common architecture choice for the ADC. However, low power dissipation dic
Yun-Shiang Shu, Pao-Cheng Chiu MediaTek, Hsinchu, Taiwan A low-power a
ISSCC 2019 Session 20 Data Converters
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC
Lu Jie, Boyi Zheng, Michael P. Flynn
Noise-Shaping SAR (NS-SAR) is an emerging ADC architecture that offers both high resolution and high energy efficiency. State-of-the-art NS-SAR ADCs eliminate the need for op-amps, which relaxes design complexity and tech
University of Michigan, Ann Arbor, MI
ISSCC 2019 Session 20 Data Converters
A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC with Passive Signal-Residue Summation in 14nm FinFET
Ying-Zu Lin*, Chin-Yu Lin*, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu
applications due to their low power and small area. SNR of 60-70dB is necessary to meet the noise budget for the downlink chain in the 802.11 ac/ax standards. Comparator noise and quantization noise are typically the dom
MediaTek, Hsinchu, Taiwan *Equally-Credited Authors (ECAs) SAR ADCs ar
ISSCC 2019 Session 20 Data Converters
A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step
Maarten Baert, Wim Dehaene
Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs
KU Leuven, Heverlee, Belgium
ISSCC 2018 Session 22 Data Converters
A 16b 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving <-67dBc IM3 Within DC-to-6GHz Tunable Passbands
Shiyu Su, Mike Shuo-Wei Chen
The agile allocation of signal bands over RF frequencies and high in-band spectral purity (both SFDR and NSD) can enable higher-order modulation in highthroughput flexible wireless/wireline transmitters, where signals ar
University of Southern California, Los Angeles, CA
ISSCC 2018 Session 22 Data Converters
A 16b 6GS/s Nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS
Chi-Hung Lin, Koon Lun Jackie Wong, Tae-Youn Kim, Guangxi Ray Xie,
over a wide bandwidth while consuming low power and small area [1] - [6]. In this work, a 16b 6GS/s Nyquist current-steering DAC in 16nm CMOS is presented. Utilizing bounded INL calibration and thermometer DEM to tackle
Donald Major, Greg Unruh, Sunny Raj Dommaraju, Hans Eberhart, Ardie Ve
ISSCC 2018 Session 22 Data Converters
A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at Nyquist in 14nm CMOS FinFET
Lukas Kull1, Danny Luu1,2, Christian Menolfi1, Matthias Braendli1,
Alessandro Cevrero1, Ilter Ozkaya1,3, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland; 3EPFL, Lausanne, Switzerland 1 2 Optical communication standards, such as ITU
Pier Andrea Francese1, Thomas Morf1, Marcel Kossel1,
ISSCC 2018 Session 14 Data Converters
A Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL and calibration noise (the larger μe, the faster calibration but higher calibration noise).
Hongxing Li1, Mark Maddox1, Michael C. W. Coln1, William Buckley2,
Derek Hummerston3, Naveed Naeem1 The ADC core, which implements this technique, is shown in Fig. 14.7.3. The framework is a pipelined SAR ADC architecture [3] to extend the acquisition time. The first stage has 11b resol
ISSCC 2018 Session 14 Data Converters
A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator
Sung-En Hsieh, Chih-Cheng Hsieh
With advanced DAC switching [1-3] and low-power comparator [4] techniques, the successive-approximation register (SAR) ADC demonstrates convincing performance with technology development for internet-of-everything (IoE)
National Tsing Hua University, Hsinchu, Taiwan
ISSCC 2018 Session 14 Data Converters
A 280μW Dynamic-Zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
Shoubhik Karmakar1, Burak Gönen1, Fabio Sebastiano1,
Robert Van Veldhoven2, Kofi A. A. Makinwa1 Delft University of Technology, Delft, The Netherlands NXP Semiconductors, Eindhoven, The Netherlands 1 2 Micro-power ADCs with high linearity and dynamic range (DR) are require
ISSCC 2018 Session 14 Data Converters
A 1.1mW 200kS/s Incremental ΔΣ ADC with a DR of 91.5dB Using Integrator Slicing for Dynamic Power Reduction
Patrick Vogelmann, Michael Haas, Maurits Ortmanns
Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various tasks such as averaging-based analysis or lock-in
University of Ulm, Ulm, Germany
ISSCC 2018 Session 14 Data Converters
A 13-ENOB 2nd-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure
Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun
The noise-shaping (NS) SAR ADC is an emerging hybrid architecture that achieves high resolution and power-efficiency simultaneously by combining the merits of the SAR ADC and the ΔΣADC, making it attractive to sensor rea
University of Texas, Austin, TX
ISSCC 2018 Session 14 Data Converters
A 15.2-ENOB Continuous-Time ΔΣ ADC for a 7.3μW 200mVpp-Linear-Input-Range Neural Recording Front-End
Hariprasad Chandrakumar, Dejan Marković
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to advance deep brain stimulation (DBS) therapies. However, stimulation generates large artifacts (~100mV) at the recording sites that satu
University of California, Los Angeles, CA
ISSCC 2018 Session 14 Data Converters
A 50MHz-BW Continuous-Time ΔΣ ADC with Dynamic Error Correction Achieving 79.8dB SNDR and 95.2dB SFDR
Tao He1, Michael Ashburn2, Stacy Ho2, Yi Zhang1, Gabor Temes1
MediaTek, Woburn, MA 1 2 Continuous-time ΔΣ modulators (CTDSMs) are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requi
Oregon State University, Corvallis, OR
ISSCC 2017 Session 28 Data Converters
A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim,
g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and highresolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the b
Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro
ISSCC 2017 Session 28 Data Converters
A 78.5dB-SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating up to 75MS/s with 24.9mW Power Consumption in 65nm CMOS
Hongda Xu1, Yongda Cai1, Ling Du2, Yuan Zhou3, Benwei Xu1,
Irvine, CA 4 Southern Methodist University, Dallas, TX 1 2 High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon
Datao Gong4, Jingbo Ye4, Yun Chiu1 University of Texas at Dallas, Rich
ISSCC 2017 Session 28 Data Converters
A 10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET
Lukas Kull1, Danny Luu1,2, Christian Menolfi1, Matthias Braendli1,
Alessandro Cevrero1, Ilter Ozkaya1, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland ETH Zurich, Zurich, Switzerland 1 2 High-speed SAR ADCs became popular with modern CMOS technologies because of t
Pier Andrea Francese1, Thomas Morf1, Marcel Kossel1, Hazar Yueksel1,
ISSCC 2017 Session 28 Data Converters
A 12b 330MS/s Pipelined-SAR ADC with PVTStabilized Dynamic Amplifier Achieving <1dB SNDR Variation
Hai Huang1, Sudipta Sarkar1, Brian Elies2, Yun Chiu1
Texas Instruments, Dallas, TX 1 2 In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements.
University of Texas at Dallas, Richardson, TX
ISSCC 2017 Session 28 Data Converters
A 125MHz-BW 71.9dB-SNDR VCO-Based CT ΔΣ ADC with Segmented Phase-Domain ELD Compensation in 16nm CMOS
Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn
MediaTek, Woburn, MA High-BW continuous-time ΔΣ modulators (CTDSMs), which directly inject excess loop delay compensation (ELDC) at the quantizer input, suffer from the over-range issue due to the 1+αz-1 transfer functio
ISSCC 2017 Session 28 Data Converters
An 11.4mW 80.4dB-SNDR 15MHz-BW CT Delta-Sigma Modulator Using 6b Double-Noise-Shaped Quantizer
Taewook Kim, Changsok Han, Nima Maghari
Quantizers are key building blocks in both continuous-time (CT) and discrete-time (DT) delta-sigma modulators (DSMs). Among various types of quantizers, noiseshaping quantizers such as VCO-based quantizers and noise-shap
University of Florida, Gainesville, FL
ISSCC 2017 Session 28 Data Converters
A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter
Chun-Cheng Liu, Mu-Chen Huang
The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power effici
MediaTek, Hsinchu, Taiwan
ISSCC 2017 Session 16 Data Converters
A 12b 10GS/s Interleaved Pipeline ADC in 28nm CMOS Technology
Siddharth Devarajan1, Larry Singer1, Dan Kelly1, Steve Kosic2, Tao Pan1,
Jose Silva1, Janet Brunsilius2, Daniel Rey-Losada2, Frank Murden3, Carroll Speir3, Jeff Bray2, Eric Otte1, Nevena Rakuljic2, Phil Brown3, Todd Weigandt2, Qicheng Yu1, Donald Paterson1, Corey Petersen2, Jeffrey Gealow1 An
ISSCC 2017 Session 16 Data Converters
A 10b DC-to-20GHz Multiple-Return-to-Zero DAC with >48dB SFDR
Lucas Duncan1, Brian Dupaix1, Jamin McCue1, Brandon Mathieu1,
towards mm-wave frequencies has increased the demand for UWB DACs with minimal spurious emissions. At mm-wave, intra-DAC dynamic timing and data errors consume a significant portion of the clock period, degrading SFDR. P
Matthew LaRue1, Mesfin Teshome2, Myung-Jun Choe2, Waleed Khalil1 Ohio
ISSCC 2017 Session 16 Data Converters
An 8GS/s Time-Interleaved SAR ADC with Unresolved Decision Detection Achieving -58dBFS Noise and 4GHz Bandwidth in 28nm CMOS
John P. Keane1, Nathaniel J. Guilar1, Dusan Stepanovic1,2,
Bernd Wuppermann1, Charles Wu1, Cheongyuen W. Tsang1,3, Robert Neff1, Ken Nishimura1 Keysight Technologies, Santa Clara, CA 1 now with Apple, Cupertino, CA 3 now with Adecco, Mountain View, CA compared using an XNOR gate
ISSCC 2017 Session 16 Data Converters
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration
Chi-Hang Chan1, Yan Zhu1, Iok-Meng Ho1, Wai-Hong Zhang1,
Wireless communication systems and Ethernet networks call for moderateresolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardwar
Seng-Pan U1,2, Rui Paulo Martins1,3 University of Macau, Macao, China
ISSCC 2017 Session 16 Data Converters
A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz
Christophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi,
Bob Verbruggen, John Mcgrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley Xilinx, Dublin, Ireland Direct-RF synthesis has gained increasing attention in r
ISSCC 2017 Session 16 Data Converters
A 9GS/s 1GHz-BW Oversampled Continuous-Time Pipeline ADC Achieving -161dBFS/Hz NSD
Hajime Shibata1, Victor Kozlov1, Zexi Ji1, Asha Ganesan2, Haiyang Zhu2, Donald Paterson2
front-end by a switchedcapacitor circuit and all internal signals are processed in discrete-time (DT) even though the front-end sampler introduces artifacts such as aliasing, noise folding, and high-peak ADC driving curr
Analog Devices, Toronto, Canada Analog Devices, Wilmington, MA 1 2 In
ISSCC 2017 Session 16 Data Converters
A 13b 4GS/s Digitally Assisted Dynamic 3-Stage Asynchronous Pipelined-SAR ADC
Bruno Vaz1, Adrian Lynam1, Bob Verbruggen1, Asma Laraba2,
Conrado Mesadri1, Ali Boumaalif3, John Mcgrath3, Umanath Kamath1, Ronnie De Le Torre1, Alvin Manlapat1, Daire Breathnach3, Christophe Erdmann1, Brendan Farley1 Xilinx, Dublin, Ireland Xilinx, San Jose, CA 3 Xilinx, Cork,
ISSCC 2016 Session 27 Data Converters
A 0.076mm2 12b 26.5mW 600MS/s 4×-Interleaved Subranging SAR-ΔΣ ADC with On-Chip Buffer in 28nm CMOS switch, is parasitic sensitive. Scaling of the LSB capacitance is therefore dictated by the parasitic capacitance of a minimum size switch instead of kT/C noise requirements. In deep-submicron technologies, this usually leads to a significantly larger core area with respect to a CR-DAC.
Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani, To exploit the CS-DAC area advantage in the reference
competitive core area a segmented SAR-DAC architecture is adopted using a CSDAC for the 4 MSBs and a CR-DAC for the remaining 6 LSBs (Fig. 27.8.2). The parasitic insensitive 6 LSBs can be scaled down as in a conventional
ISSCC 2016 Session 27 Data Converters
A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration
Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs ar
National Taiwan University, Taipei, Taiwan
ISSCC 2016 Session 27 Data Converters
A 4GS/s 13b Pipelined ADC with Capacitor and Amplifier Sharing in 16nm CMOS
Jiangfeng Wu1,2, Acer Chou1, Tianwei Li1, Rong Wu1, Tao Wang1,
Giuseppe Cusmai1, Sha-Ting Lin3, Cheng-Hsun Yang3, Gregory Unruh1, Sunny Raj Dommaraju1, Mo M. Zhang1, Po Tang Yang3, Wei-Ting Lin3, Xi Chen1, Dongsoo Koh1, Qingqi Dou1, H. Mohan Geddada1, Juo-Jung Hung1, Massimo Brandol
ISSCC 2016 Session 27 Data Converters
A 4GS/s Time-Interleaved RF ADC in 65nm CMOS with 4GHz Input Bandwidth
Matt Straayer1, Jim Bales2, Dwight Birdsall2, Denis Daly1,
Phillip Elliott2, Bill Foley1, Roy Mason2, Vikas Singh3, Xuejin Wang2 Maxim Integrated Products, North Chelmsford, MA, Maxim Integrated Products, Fort Collins, CO, 3 Maxim Integrated Products, San Jose, CA 1 2 The perfor
ISSCC 2016 Session 27 Data Converters
A 0.35mW 12b 100MS/s SAR-Assisted Digital Slope ADC in 28nm CMOS Chun-Cheng Liu
MediaTek, Hsinchu, Taiwan
In recent years, the operation speed of SAR ADCs has improved with the scaling of CMOS technology. SAR ADCs achieve a few hundreds of MS/s with 8-to-10b resolution. The SNR of high-speed SAR ADCs is mainly dominated by c
ISSCC 2016 Session 27 Data Converters
Area-Efficient 1GS/s 6b SAR ADC with ChargeInjection-Cell-Based DAC
Kyojin D. Choo, John Bell, Michael P Flynn
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is
University of Michigan, Ann Arbor, MI
ISSCC 2016 Session 27 Data Converters
An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS
Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo
The successive-approximation-register (SAR) architecture is well-known for its high power efficiency in medium-resolution A/D conversions. Together with time interleaving, it can challenge the regime of flash ADCs in hig
MediaTek, Hsinchu, Taiwan
ISSCC 2016 Session 27 Data Converters
A 12b 2GS/s Dual-Rate Hybrid DAC with Pulsed Timing-Error Pre-Distortion and In-Band Noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS
Shiyu Su, Mike Shuo-Wei Chen
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its
University of Southern California, Los Angeles, CA
ISSCC 2016 Session 15 Data Converters
A 22.3b 1kHz 12.7mW Switched-Capacitor ΔΣ Modulator with Stacked Split-Steering Amplifiers
Matthias Steiner1, Nigel Greer2
West Silicon EURL, Hottot les Bagues, France 1 2 Efforts to improve the resolution and power-efficiency of ADCs continue unabated, as is well documented in [2]. Although the number of new switchedcapacitor (SC) ADC publi
ams AG, Unterpremstaetten, Austria,
ISSCC 2016 Session 15 Data Converters
A 1.65mW 0.16mm2 Dynamic Zoom-ADC with 107.5dB DR in 20kHz BW
Burak Gönen1, Fabio Sebastiano1, Robert van Veldhoven2, Kofi A. A. Makinwa1
stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and en
Delft University of Technology, Delft, The Netherlands, NXP Semiconduc
ISSCC 2016 Session 15 Data Converters
A 160MHz-BW 72dB-DR 40mW Continuous-Time ΔΣ Modulator in 16nm CMOS with Analog ISIReduction Technique
Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai
baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. Fo
MediaTek, Hsinchu, Taiwan Continuous-time delta-sigma modulators (CT-D
ISSCC 2016 Session 15 Data Converters
A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS
Yunzhi Dong1, Jialin Zhao1, Wenhua Yang1, Trevor Caldwell2,
Cambridge, MA 1 2 The width of RF bands commonly used for cellular telecommunications has grown from 35-to-75MHz for 2G/3G/4G platforms to 100-to-200MHz for today’s LTE, and the desire for relaxed image-rejection filteri
Hajime Shibata2, Richard Schreier2, Qingdong Meng3, Jose Silva1, Donal
ISSCC 2016 Session 15 Data Converters
A 280µW 24kHz-BW 98.5dB-SNDR Chopped Single-Bit CT ΔΣM Achieving <10Hz 1/f Noise Corner Without Chopping Artifacts
Sujith Billa, Amrith Sukumaran, Shanthi Pavan
IIT Madras, Chennai, India Many industrial applications require high-resolution ADCs whose low-frequency performance is important. CTDSMs are attractive due to their implicit antialiasing and resistive inputs. However, t
ISSCC 2016 Session 15 Data Converters
A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM
Blazej Nowacki1,2, Nuno Paulino1,2, Joao Goes1,2
DEE, FCT, Universidade NOVA de Lisboa, Caparica, Portugal, CTS-UNINOVA, Caparica, Portugal 1 2 ΔΣM performance can be improved by using MASH or SMASH structures to obtain higher-order noise shaping [1]. They have better
ISSCC 2016 Session 15 Data Converters
A 2.2GHz Continuous-Time ΔΣ ADC with -102dBc THD and 25MHz BW
Lucien Breems1, Muhammed Bolatkale1, Hans Brekelmans1,
Shagun Bajoria1, Jan Niehof1, Robert Rutten1, Bert Oude-Essink2, Franco Fritschij2, Jagdip Singh2, Gerard Lassche2 NXP Semiconductors, Eindhoven, The Netherlands, Catena Microelectronics, Delft, The Netherlands 1 2 The t
ISSCC 2016 Session 15 Data Converters
A 24.7mW 45MHz-BW 75.3dB-SNDR SARAssisted CT ΔΣ Modulator with 2nd-Order Noise Coupling in 65nm CMOS
Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu
Technology advancement has recently made it attractive to replace the flash quantizer (QTZ) in a multibit ΔΣ modulator by an asynchronous successiveapproximation-register (ASAR) QTZ to improve the overall power efficienc
University of Texas, Dallas, TX
ISSCC 2015 Session 26 Data Converters
A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4×-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique
Hyeok-Ki Hong1, Hyun-Wook Kang1, Dong-Shin Jo1, Dong-Suk Lee2,
(TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching
Yong-Sang You2, Yong-Hee Lee2, Ho-Jin Park2, Seung-Tak Ryu1 KAIST, Dae
ISSCC 2015 Session 26 Data Converters
A 5GS/s 150mW 10b SHA-Less Pipelined/SAR Hybrid ADC in 28nm CMOS
Massimo Brandolini1, Young Shin1, Karthik Raviprakash1, Tao Wang1,
Rong Wu1, Hemasundar M. Geddada1, Yen-Jen Ko2, Yen Ding2, Chun-Sheng Huang2, Wei-Ta Shih2, Ming-Hung Hsieh2, Wei-Te Chou1, Tianwei Li1, Ayaskant Shrivastava1, Yi-Chun Chen1, Juo-Jung Hung1, Giuseppe Cusmai1, Jiangfeng Wu
ISSCC 2015 Session 26 Data Converters
A 5.5mW 6b 5GS/s 4×-Interleaved 3b/cycle SAR ADC in 65nm CMOS
Chi-Hang Chan1, Yan Zhu1, Sai-Weng Sin1,
Seng-Pan U1,2, R. P. Martins1,3 University of Macau, Macao, China, Synopsys, Macao, China, 3 Instituto Superior Tecnico, Universidade de Lisboa, Portugal 1 2 Communication devices such as 60GHz-band receivers and serial