ISSCC 2015
Session 26
Data Converters
A 21fJ/conv-step 9 ENOB 1.6GS/s 2× Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS
taken advantage of timeinterleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexit
ISSCC 2015
Session 26
Data Converters
An 800MS/s 10b/13b Receiver for 10GBASE-T Ethernet in 28nm CMOS
Nitz Saputra3, Qiongna Zhang1, Jeff Riley1, Han Yan1, Mattia Introini1, Sijia Wang1, Christopher M. Ward1, Jan Westra1, Jiansong Wan1, Klaas Bult1 Broadcom, Bunnik, The Netherlands, Broadcom, Irvine, CA, 3Qualcomm, San D
ISSCC 2015
Session 26
Data Converters
A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC Utilizing a Redundancy-Facilitated Background Error-Detection-and-Correction Scheme
g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 1
ISSCC 2015
Session 26
Data Converters
A 1mW 71.5dB SNDR 50MS/s 13b Fully Differential Ring-Amplifier-Based SAR-Assisted Pipeline ADC
The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [1]. Consisting of two low-resolution charge-redistribution SAR ADCs coupled by a residue amplifier, a SAR-assisted pipeline ADC relax
ISSCC 2015
Session 15
Data Converters
A 90dB-SFDR 14b 500MS/s BiCMOS Switched-Current Pipelined ADC
on data converters. To enable base stations with multi-carrier functionality, ADCs in the receive path need high sample rates with superior SFDR across 100s of MHz and several decades of input signal power. Furthermore,
ISSCC 2015
Session 15
Data Converters
A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS
NXP Semiconductors, Eindhoven, The Netherlands 1 2 Successive-approximation-register (SAR) analog-to-digital converters (ADCs) have generated a great deal of interest in the past several years. While most of the recent w
ISSCC 2015
Session 15
Data Converters
A 12b 250MS/s Pipelined ADC with Virtual Ground Reference Buffers
High-performance op-amps in a switched-capacitor pipelined ADC consume high power to meet accuracy and speed requirements. This is aggravated by the decrease in intrinsic transistor gain and voltage headroom in nanoscale
ISSCC 2015
Session 15
Data Converters
A 0.6V 1.17ps PVT-Tolerant and Synthesizable Time-to-Digital Converter Using Stochastic Phase Interpolation with 16× Spatial Redundancy in 14nm FinFET Technology
timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of qu
ISSCC 2015
Session 15
Data Converters
A 0.8V 10b 80kS/s SAR ADC with Duty-Cycled Reference Generation
sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensi
ISSCC 2015
Session 15
Data Converters
A 115dB-DR Audio DAC with –61dBFS Out-of-Band Noise
Delectronics, Enschede, The Netherlands, 3 Teledyne DALSA Semiconductors, Enschede, The Netherlands 1 2 Out-of-band noise (OBN) is troublesome in analog circuits that process the output of a noise-shaping audio DAC. It c
ISSCC 2015
Session 15
Data Converters
A 4.5mW CT Self-Coupled ΔΣ Modulator with 2.2MHz BW and 90.4dB SNDR Using Residual ELD Compensation
front-end filter design for wireless communication applications. To achieve high resolution (DR>90dB) and low power dissipation (FoMs>170dB), architecture selection and circuit techniques are the main design issues. In [
ISSCC 2015
Session 15
Data Converters
An 85dB-DR 74.6dB-SNDR 50MHz-BW CT MASH ΔΣ Modulator in 28nm CMOS
MediaTek, Woburn, MA 1 2 A multi-stage noise-shaping (MASH) architecture is an attractive approach for its aggressive noise-shaping capability and relaxed stability requirements. However, in practice the quantization noi
ISSCC 2014
Session 29
Data Converters
A 14b 1GS/s RF Sampling Pipelined ADC with Background Calibration Fig. 29.3.4, and the LMS algorithm is used to estimate the correction coefficients using the recursive formula: Gen + k = Gen k − μ × Vd>n − k @ × Vd>n − k @ × Gen k − VR >n@
Scott Puckett1, Bryce Gray1, Carroll Speir1, Jonathan Lanford1, David Jarman1, Janet Brunsilius2, Peter Derounian1, Brad Jeffries1, Ushma Mehta1, Matt McShea1, Ho-Young Lee3 Where Vd is the dither value, VR is the residu
ISSCC 2014
Session 29
Data Converters
A 235mW CT 0-3 MASH ADC Achieving -167dBFS/Hz NSD with 53MHz BW
ADCs in wireless communication infrastructure is increased bandwidth with little or no relaxation in noise density or power consumption. The historical expectation of system designers is a noise spectral density (NSD) of
ISSCC 2014
Session 29
Data Converters
A 5mW CT ΔΣ ADC with Embedded 2nd-Order Active Filter and VGA Achieving 82dB DR in 2MHz BW
IIT Madras, Chennai, India Conventional continuous-time delta-sigma modulator (CTDSM) architectures do not allow independent control of the shape and bandwidth of the signal transfer function (STF), since the STF is simp
ISSCC 2014
Session 22
Data Converters
A 14b 4.6GS/s RF DAC in 0.18µm CMOS for Cable Head-End Systems
Paul Kalthoff3, Ajay Kuckreja4, Geir Ostrem3 Maxim Integrated, North Chelmsford, MA, 2Maxim Integrated, Woodstock, GA, Maxim Integrated, Colorado Springs, CO, 4Maxim Integrated, Boulder, CO 1 the other input is driven to
ISSCC 2014
Session 22
Data Converters
A 2.2GS/s 7b 27.4mW Time-Based Folding-Flash ADC with Resistively Averaged Voltage-to-Time Amplifiers
as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, whic
ISSCC 2014
Session 22
Data Converters
A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS
Sarah Verhaeren1, Emmanuel Rouat1, Pascal Urard1, Stéphane Le Tual1, Dimitri Goguet1, Caroline Lelandais-Perrault2, Philippe Benabes2 STMicroelectronics, Crolles, France, Supélec, Gif-sur-Yvette, France 1 2 Today’s appli
ISSCC 2014
Session 22
Data Converters
A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration
SARs are one of the most energy-efficient ADC architectures for medium resolution and low-to-medium speed. To improve the limited bandwidth of SAR ADCs, the time-interleaved (TI) structure is often used [1,2]. However, T
ISSCC 2014
Session 22
Data Converters
A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology
France 1 After quantization, each SAR stores its 6b word in 2 ping-pong 512-word RAMs running at 10GHz/8/2=625MHz. The total 8K words are finally read at low speed through a JTAG controller. The chip is fabricated in 28n
ISSCC 2014
Session 22
Data Converters
A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI
Low-power time-interleaved ADCs with high sampling rates of over 10GS/s are in high demand for wireline communication systems. However, the timeinterleaved channels suffer from process mismatch, particularly for timing s
ISSCC 2014
Session 22
Data Converters
A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS
Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1, Toke Meyer Andersen1, Yusuf Leblebici2 IBM Research, Rüschlikon, Switzerland, EPFL, Lausanne, Switzerland 1 2 Forthcoming optical communication standa
ISSCC 2014
Session 11
Data Converters
A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz
Govert Geelen, Harrie Gunnink, Yongjie Jin, Mustafa Kaba, Kerong Luo, Edward Paulus, Bang Pham, William Relyveld, Peter Zijlstra Integrated Device Technology, Eindhoven, The Netherlands Advanced wireless cellular infrast
ISSCC 2014
Session 11
Data Converters
A 21mW 15b 48MS/s Zero-Crossing Pipeline ADC in 0.13µm CMOS with 74dB SNDR
Kevin Guay2, Thomas Thurston2, Hae-Seung Lee3, Kush Gulati1, Matthew Straayer2 Maxim Integrated, San Jose, CA, Maxim Integrated, North Chelmsford, MA, 3 Massachusetts Institute of Technology, Cambridge, MA 1 2 Pipeline A
ISSCC 2014
Session 11
Data Converters
A 100MS/s 10.5b 2.46mW Comparator-less Pipeline ADC Using Self-Biased Ring Amplifiers
Samsung Electronics, Yongin, Korea 1 2 Pipelined ADCs require accurate amplification; however traditional OTAs limit power efficiency since they require high quiescent current for slewing. In addition, it is difficult to
ISSCC 2014
Session 11
Data Converters
A 1.5mW 68dB SNDR 80MS/s 2× Interleaved SARAssisted Pipelined ADC in 28nm CMOS
sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design target
ISSCC 2014
Session 11
Data Converters
A 10b 0.6nW SAR ADC with Data-Dependent Energy Savings Using LSB-First Successive Approximation
ADCs used in medical and industrial monitoring often transduce signals with short bursts of high activity followed by long idle periods. Examples include biopotential, sound, and accelerometer waveforms. Current approach
ISSCC 2014
Session 11
Data Converters
A 0.85fJ/conversion-step 10b 200kS/s Subranging SAR ADC in 40nm CMOS
Analog-to-digital converters (ADC) are extensively used in wireless sensor networks and healthcare electronic devices to monitor long-term signal conditions. It is essential to prolong battery life in these applications
ISSCC 2014
Session 11
Data Converters
An Oversampled 12/14b SAR ADC with Noise Reduction and Linearity Enhancements Achieving up to 79.1dB SNDR
Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environment
ISSCC 2013
Session 26
Data Converters
A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over Entire Nyquist Bandwidth
Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at t
ISSCC 2013
Session 26
Data Converters
A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
veryhigh-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings [1], and (b) in high-speed, lowresolution applications [2, 3] in which the SAR’s low power
ISSCC 2013
Session 26
Data Converters
An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement
consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in
ISSCC 2013
Session 26
Data Converters
A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
Christian Menolfi1, Matthias Braendli1, Marcel Kossel1, Thomas Morf1, Toke Meyer Andersen1, Yusuf Leblebici2 IBM Research, Rüschlikon, Switzerland, 2EPFL, Lausanne, Switzerland 1 Next-generation digital high-speed links
ISSCC 2013
Session 26
Data Converters
A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction the chop PRBS. BUF1 and BUF2 modulate the chop drive signal at the bases of Q1–Q4 with a level-shifted version of the input signal. This bootstrapping ensures that M1 and M2 have a reasonably constant Vgd for improved linearity and reduced thermal transients.
Valentin Abramzon1, Guenter Steinbach1, John P. Keane1, Bernd Wuppermann1, Mathew Clayson1, Matthew Martin2, Rizwan Pasha2, Edda Peeters3, Annemie Jacobs3, Filip Demarsin3, Adnan Al-Adnani3, Peter Brandt3 The analog dith
ISSCC 2013
Session 26
Data Converters
An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS
Alessandro Murroni1, Gerard van der Weide1, Yu Lin1, Ludo Alvado2, Frederic Darthenay2, Yannick Fregeais2 NXP Semiconductors, Eindhoven, The Netherlands, NXP Semiconductors, Caen, France 1 2 Over the last years several l
ISSCC 2013
Session 26
Data Converters
A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications
throughout the network infrastructure. A wide array of standards has been developed supporting 10GE over both fiber and copper media. A particularly challenging standard is Long Reach Multimode (LRM), which targets insta
ISSCC 2013
Session 15
Data Converters
Adaptive Cancellation of Gain and Nonlinearity Errors in Pipelined ADCs
ΔΣ modulators and pipelined ADCs, accurately transferring voltages in sampled-data form, regardless of opamp gain and nonlinearity, has been one of the most challenging issues that analog designers have faced. To date, i
ISSCC 2013
Session 15
Data Converters
A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS
Applications of wireless sensor networks and biomedical devices frequently require an ADC with medium resolution (8 to 12b) running at hundreds of kS/s to a few MS/s. Successive-approximation register (SAR) ADCs show con
ISSCC 2013
Session 15
Data Converters
A 20b Clockless DAC with Sub-ppm-Linearity 7.5nV/√Hz-Noise and 0.05ppm/°C-Stability
Douglas Chisholm1, Denise T. Lee1 Analog Devices, Edinburgh, United Kingdom, Analog Devices, Wilmington, MA 1 2 DACs without continuous clocking are often favored in applications such as medical imaging and scientific in
ISSCC 2013
Session 15
Data Converters
A 6.3μW 20b Incremental Zoom-ADC with 6ppm INL and 1μV Offset
Delft University of Technology, Delft, The Netherlands 1 2 Incremental analog-to-digital converters (ADCs) can be applied in many instrumentation applications, such as the readout of bridge transducers and smart sensors
ISSCC 2013
Session 15
Data Converters
A 1V 14b Self-Timed Zero-Crossing-Based Incremental ΔΣ ADC
This paper introduces a clock-free self-timed incremental ΔΣ ADC. Unlike conventional ΔΣ ADCs, it does not require a dedicated clock signal, thus saving energy and reducing system complexity. As such, it has similar adva
ISSCC 2013
Session 15
Data Converters
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noise
utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. How
ISSCC 2013
Session 15
Data Converters
A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction
Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs
ISSCC 2013
Session 15
Data Converters
A 28fJ/conv-step CT ΔΣ Modulator with 78dB DR and 18MHz BW in 28nm CMOS Using a Highly Digital Multibit Quantizer
compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially signific
ISSCC 2012
Session 8
Data Converters
A 20mW 61dB SNDR (60MHz BW) 1b 3rd-Order Continuous-Time Delta-Sigma Modulator Clocked at 6GHz in 45nm CMOS
ADCs in deep-submicron processes [1-4]. The maximum sampling rate is set by Excess Loop Delay (ELD) considerations. ELD comprises the comparator latency, feedback DAC delay (DEM delay etc.) and any additional delay due t
ISSCC 2012
Session 8
Data Converters
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS
We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A most
ISSCC 2012
Session 8
Data Converters
A 72dB-DR ΔΣ CT Modulator Using Digitally Estimated Auxiliary DAC Linearization Achieving 88fJ/conv in a 25MHz BW
modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3rd or 4th-order loop-filters [1,2]. In order to improve power efficiency, circuit and a
ISSCC 2012
Session 8
Data Converters
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC Using Residue-Cancelling VCO-Based Quantizer
conversion presents an attractive means of implementing high-bandwidth oversampling ADCs [1,2]. They exhibit inherent noise-shaping properties and can operate at low supply voltages and high sampling rates [1-3]. However
ISSCC 2012
Session 8
Data Converters
A DC-to-1GHz Tunable RF ΔΣ ADC Achieving DR = 74dB and BW = 150MHz at f0 = 450MHz Using 550mW
The ultimate ADC for receiver applications would be one that converts any desired RF signal directly into digital form so that the rest of the signal chain enjoys accurate and flexible digital signal processing and CMOS
ISSCC 2012
Session 8
Data Converters
A 12mW Low-Power Continuous-Time Bandpass ΔΣ Modulator with 58dB SNDR and 24MHz Bandwidth at 200MHz IF
Analog Devices, Wilmington, MA 1 A continuous-time bandpass ΔΣ modulator (CTBPDSM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in the digital backend and also decreases the comple