ISSCC 2012
Session 8
Data Converters
An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs
avoids the traditional problems of direct-conversion receivers, such as EVM degradation due to IQ imbalance, 2nd-order intermodulation, and AGC interaction with DC offset correction settling. Our target application is a
ISSCC 2012
Session 27
Data Converters
A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V Two-Step Pipelined ADC in 0.13µm CMOS
National Semiconductor, Santa Clara, CA which may be done simply by changing the gain combination in the two cascaded gain stages. Such optimization may lead to further reduction in power consumption and also allow for l
ISSCC 2012
Session 27
Data Converters
A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step
However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates [1,2]. An
ISSCC 2012
Session 27
Data Converters
A 70dB DR 10b 0-to-80MS/s Current-Integrating SAR ADC with Adaptive Dynamic Range
to develop more innovative systems to improve performance. Remarkable improvements have been recently realized on charge-domain SAR ADCs to reach the speed of a few tens of MS/s with medium resolution and low power consu
ISSCC 2012
Session 27
Data Converters
A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC
In recent years, charge-redistribution SAR (Successive Approximation) ADCs have exhibited the highest conversion efficiencies for ADCs with moderate resolution and bandwidth [1-3]. For effective resolutions beyond 10b or
ISSCC 2012
Session 27
Data Converters
A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS
Renesas Electronics, Kawasaki, Japan 1 2 In recent years ADC research has resulted in impressive advances in power efficiency. SAR ADCs have reached energies per conversion step below 10fJ, but only at rather low samplin
ISSCC 2012
Session 27
Data Converters
A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators
Time-to-digital converters (TDCs) were historically used in laser range-finding, automatic test equipment, and timing jitter measurements, but recent developments in the design of high-resolution TDCs have paved the way
ISSCC 2012
Session 27
Data Converters
A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC
The opamps in a switched-capacitor (SC) pipelined ADC provide the functions of sample-and-hold, residue generation, and residue amplification [1,2]. High-performance opamps that meet the requirements for dc gain, speed,
ISSCC 2012
Session 27
Data Converters
Ring Amplifiers for Switched-Capacitor Circuits
design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power
ISSCC 2012
Session 27
Data Converters
A 14b 3/6GHz Current-Steering RF DAC in 0.18µm CMOS with 66dB ACLR at 2.9GHz
The growth in communications coupled with the move towards multi-carrier, multi-band, multi-standard radio transmitters have helped drive high-speed digital-to-analog converter (DAC) technology for over a decade. The cri
ISSCC 2011
Session 27
Data Converters
A 108dB-DR 120dB-THD and 0.5Vrms Output Audio DAC with Inter-Symbol-Interference-Shaping Algorithm in 45nm CMOS
fine-resolution quantization to reduce the out-of-band noise (OBN), reduce jitter sensitivity, and simplify analog filtering. Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g
ISSCC 2011
Session 27
Data Converters
A 120dB-SNR 100dB-THD+N 21.5mW/Channel Multibit CT ΔΣ DAC
Analog Devices, Wilmington, MA Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low po
ISSCC 2011
Session 27
Data Converters
A 1.7mW 11b 1-1-1 MASH ΔΣ Time-to-Digital Converter
SCK-CEN, Mol, Belgium 3 KH Kempen, Geel, Belgium The frequency of the relaxation oscillator can be expressed as IREF/(VREF·2C). By correlating VREF and IREF as VREF = IREF·R, its frequency becomes only dependant on passi
ISSCC 2011
Session 27
Data Converters
A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140µW
This third-order ΔΣ modulator [1, 2], suitable for high-resolution low-power sensor systems, consumes 140µW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step The DACs u
ISSCC 2011
Session 27
Data Converters
A 250mV 7.5µW 61dB SNDR CMOS SC ΔΣ Modulator Using a Near-Threshold-Voltage-Biased CMOS Inverter Technique
One of the most continuous trends in solid-state circuits is the decrease in power supply as a direct consequence of technology scaling. The fact that Vt does not scale linearly with supply voltage has encouraged several
ISSCC 2011
Session 27
Data Converters
A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bidirectional Single-Slope Quantizer
The aspirations for power efficient ADCs have led to many improvements in this area. In delta-sigma modulators, techniques such as VCO-based quantizer [1, 2] and time-domain quantization [3] have been proposed to enhance
ISSCC 2011
Session 27
Data Converters
An 8mW 50MS/s CT ΔΣ Modulator with 81dB SFDR and Digital Background DAC Linearization
There is ongoing effort to realize low-power ΔΣ ADCs with more than 10MHz bandwidth (BW) – especially for wireless transceivers. Besides the trend to make these ADCs more reconfigurable [1], recent advances in the design
ISSCC 2011
Session 27
Data Converters
A 4GHz CT ΔΣ ADC with 70dB DR and –74dBFS THD in 125MHz BW
2 NXP Semiconductors, Eindhoven, The Netherlands Delft University of Technology, Delft, The Netherlands In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused b
ISSCC 2011
Session 10
Data Converters
A 56GS/s 6b DAC in 65nm CMOS with 256×6b Memory
Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan Ciena, Ottawa, Canada Modern optical systems increasingly rely on DSP techniques for data transm
ISSCC 2011
Session 10
Data Converters
A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz
The current-steering DACs are commonly used in generating high-frequency signals [1-4]. A current-steering DAC comprises current cells of various sizes. Each of them contains a current source and a current switch. The DA
ISSCC 2011
Session 10
Data Converters
A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC
Applications such as sensor networks and medical monitoring often require ADCs that can digitize signals with varying bandwidth and dynamic range requirements. In energy-constrained systems, it is beneficial to adapt the
ISSCC 2011
Session 10
Data Converters
A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS
Italy 2 The successive-approximation (SA) algorithm is traditionally used for lowbandwidth applications because it requires n clock cycles or more to obtain nbit resolution. However, the use of modern nanometer CMOS tech
ISSCC 2011
Session 10
Data Converters
A 16b 80MS/s 100mW 77.6dB SNR CMOS Pipeline ADC
increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/s with a 10MHz input. With a 200MHz input, the A
ISSCC 2011
Session 10
Data Converters
An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS
Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult Broadcom, Bunnik, The Netherlands The 800MS/s 12b pipeline ADC presented here achieves a 59dB peak SNDR while consuming 105mW, resulting in an FOM of 0.18pJ/con
ISSCC 2011
Session 10
Data Converters
A 12b 1GS/s SiGe BiCMOS Two-Way TimeInterleaved Pipeline ADC drives the top-plate sampling switch (M1) and achieves high SFDR. A 20Ω resistor between M1 and the 600fF sampling capacitor improves the linearity of M1.
Marco Corsi1, David Smith1, Noam Tal2 Analog calibration techniques address the mismatches between branches. Timing skew is adjusted using a 10b DAC to supply the clock buffer power supply which changes its propagation d
ISSCC 2011
Session 10
Data Converters
A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist
many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die [1] could be simplified with a low-power 10b ADC that can digitize the e
ISSCC 2010
Session 21
Data Converters
A 40GS/s 6b ADC in 65nm CMOS
Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang Nortel, Ottawa, Canada Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G tran
ISSCC 2010
Session 21
Data Converters
A 30fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in 90nm CMOS
power-efficient ADCs. Moreover, the power-efficiency should be maintained for a wide range of sampling rates to enable system-level flexibility. Previously, the use of SAR ADCs has been proposed for low-power application
ISSCC 2010
Session 21
Data Converters
A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation
with three compensative capacitors can tolerate settling error of at least 12.5% in each bit cycle. Note the precise error tolerance range depends on where the wrong decision occurs. The amplitude of the input signal swi
ISSCC 2010
Session 21
Data Converters
A 10b 50MS/s 820µW SAR ADC with On-Chip Digital Calibration
power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static curre
ISSCC 2010
Session 21
Data Converters
A 0.06mm2 8.9b ENOB 40MS/s Pipelined SAR ADC in 65nm CMOS
In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and
ISSCC 2010
Session 21
Data Converters
A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC Achieving Over 90dB SFDR
CMOS technology scaling has opened a pathway to high-performance analogto-digital conversion in the nanometer regime, where switching is preferred over amplifying. Successive-approximation-register (SAR) is one of the co
ISSCC 2010
Session 21
Data Converters
An 18b 12.5MHz ADC with 93dB SNR
21.1.3. To allow auto-zeroing of offset and 1/f noise, additional switches are added to allow the amplified offset and 1/f noise of the first stage to be stored on the inter-stage capacitors C1 and C2. Since a full ten b
ISSCC 2010
Session 16
Data Converters
A 110dB SNR and 0.5mW Current-Steering Audio DAC Implemented in 45nm CMOS
longer battery life and lower cost. Achieving low out–of-band noise (OBN) is one of the key elements in designing inexpensive, low-power and robust audio DACs. Lowering OBN reduces the sensitivity to circuit mismatch, gl
ISSCC 2010
Session 16
Data Converters
A 1.4V Signal Swing Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing Opamp
Scaling in CMOS technologies has made the application of traditional opamp topologies increasingly difficult. In the face of decreasing voltage headroom and intrinsic device gain, designers have employed techniques such
ISSCC 2010
Session 16
Data Converters
A 10b 100MS/s 4.5mW Pipelined ADC with a Time Sharing Technique
For the applications requiring medium-to-high resolution ADCs, the pipelined architecture is considered to be the most optimal structure in terms of power consumption and area. With range overlap and redundant bit at eac
ISSCC 2010
Session 16
Data Converters
A Mostly Digital Variable-Rate Continuous-Time ADC ΔΣ Modulator
modulator is presented that consists mostly of digital circuitry. It does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a lowjitter clock. Unlike conventional ΔΣ
ISSCC 2010
Session 16
Data Converters
A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS
fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed w
ISSCC 2010
Session 16
Data Converters
A 16b 100-to-160MS/s SiGe BiCMOS Pipelined ADC with 100dBFS SFDR
The RX signal path in wireless base transceiver stations (BTS) drives the continued development of high-resolution high-speed ADCs. Such ADCs enable BTSs with software-defined and/or multi-carrier capability, such as mul
ISSCC 2010
Session 16
Data Converters
A 16b 250MS/s IF-Sampling Pipelined A/D Converter with Background Calibration
Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed Analog Devices, Greensboro, NC Wireless communication applications have driven the de
ISSCC 2009
Session 9
Data Converters
A Multirate 3.4-to-6.8mW 85-to-66dB DR GSM/Bluetooth/UMTS Cascade DT ∆ΣΜ in 90nm Digital CMOS can be adjusted according to the required sampling frequency by changing the output stage bias. The 1.5b quantizer consists of 2 comparators and a switched-capacitor network that generates a voltage shift of
Yves Rolain2, Geert Van der Plas1 for the comparator input signals. The comparator is based on a dynamic regenerative latch driving an SR latch. The reference voltage of the DAC is 0.8V. 9.8 IMEC, Leuven, Belgium Vrije U
ISSCC 2009
Session 9
Data Converters
A 20MHz BW 68dB DR CT ∆Σ ADC Based on a MultiBit Time-Domain Quantizer and Feedback Element
Edgar Sánchez-Sinencio1, Jose Silva-Martinez1, Chinmaya Mishra1,2, Lei Chen1, Erik Pankratz1 1 Texas A&M University, College Station, TX Qualcomm, San Diego, CA 2 Low-power, small-area, 20MHz-BW ADCs that can be integrat
ISSCC 2009
Session 9
Data Converters
A 1.2V 2MHz BW 0.084mm2 CT ∆Σ ADC with -97.7dBc THD and 80dB DR Using Low-latency DEM
Due to their inherent anti-aliasing properties and potential for low-power design, continuous-time (CT) ∆Σ ADCs are an indispensable component in wireless communication systems such as GSM/WCDMA, since a precise sampling
ISSCC 2009
Session 9
Data Converters
A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ∆Σ ADC with VCO-Based Integrator and Quantizer
based ADCs have become a topic of great interest due to the unique and attractive signal-processing properties they offer in the design of oversampling converters. Assuming a ring-oscillator structure, the outputs of a V
ISSCC 2009
Session 9
Data Converters
A 9b 14µW 0.06mm2 PPM ADC in 90nm Digital CMOS
University of Michigan, Ann Arbor, MI, National Semiconductor, Salem, NH As CMOS dimensions scale down, time-domain resolution of digital signals improves but the voltage resolution of analog signals degrades [1]. In thi
ISSCC 2009
Session 9
Data Converters
A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB
As intrinsic device gain and power supply voltages decrease with CMOS technology scaling, it is becoming increasingly challenging for designers of conventional opamp-based switched-capacitor circuits to meet gain and out
ISSCC 2009
Session 9
Data Converters
A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18µm CMOS Using Capacitive Charge-Pumps
pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined
ISSCC 2009
Session 9
Data Converters
A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancella
ISSCC 2009
Session 4
Data Converters
A 16b 125MS/s 385mW 78.7dB SNR CMOS Pipeline ADC
ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity, quantified by SFDR for less-than-full-scale inputs is important
ISSCC 2009
Session 4
Data Converters
A 10b 500MHz 55mW CMOS ADC
Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11b has faced speed limitations with a single channel [1] or employed interleaving, but with a relatively high power