A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18µm CMOS Using Capacitive Charge-Pumps

📋 论文概要

本文提出了一种使用电容电荷泵替代传统运放的低功耗流水线ADC，在0.18µm CMOS工艺下实现了50MS/s采样率和58dB SNDR，功耗仅9.9mW。该设计解决了传统运放功耗高的问题，同时避免了复杂校准和单端结构的局限性。

💡 主要创新点

• 采用电容电荷泵替代运放实现流水线级间增益，显著降低功耗。
• 实现了全差分结构，避免了单端或伪差分带来的线性度限制。

🏷 关键词

📄 原文摘要

pipelined ADCs, several power-efficient pipelined ADCs have recently been proposed. The most promising topologies reported thus far are those that substitute the opamp, which is the largest consumer of power in pipelined ADCs, with alternative and more power-efficient circuits. However, opamp-less pipelined ADCs thus far either: 1) require complex nonlinear calibration [1], 2) are singleended [2], 3) are pseudo-differential [3], or 4) require a sampling scheme that limits linearity (less than 8b ENOB in [3]). In this paper, a low-power pipelined ADC is presented that has significantly lower power consumption than many previous 10b ADCs in the mid-to-high speed range. The ADC does not require power-hungry opamps, and hence achieves similar power savings as in [1-3].

👥 作者与机构

Imran Ahmed1, Jan Mulder2, David A. Johns1, 1

University of Toronto, Toronto, Canada Broadcom, Bunnik, Netherlands 2 In the interest of extending battery life in mobile systems that use