A Multirate 3.4-to-6.8mW 85-to-66dB DR GSM/Bluetooth/UMTS Cascade DT ∆ΣΜ in 90nm Digital CMOS can be adjusted according to the required sampling frequency by changing the output stage bias. The 1.5b quantizer consists of 2 comparators and a switched-capacitor network that generates a voltage shift of

📋 论文概要

该论文提出了一种基于90nm数字CMOS工艺的多速率级联离散时间Delta-Sigma调制器，通过重新配置采样频率和级联结构，实现了对GSM/Bluetooth/UMTS多标准的覆盖。在3.4至6.8mW的功耗范围内，动态范围为85至66dB，有效解决了多标准接收机中的功耗与性能折衷问题。

💡 主要创新点

• 提出多速率可重构的级联离散时间Delta-Sigma调制器架构，通过改变采样频率适应不同通信标准。
• 采用动态再生锁存比较器和SR锁存器，优化了比较器输入信号处理，降低了功耗。

🏷 关键词

📄 原文摘要

Yves Rolain2, Geert Van der Plas1 for the comparator input signals. The comparator is based on a dynamic regenerative latch driving an SR latch. The reference voltage of the DAC is 0.8V. 9.8 IMEC, Leuven, Belgium Vrije Universiteit Brussel, Brussels, Belgium 3 Ghent University, Ghent, Belgium 9 ± 5()   1 2 The main advantages of discrete-time (DT) systems are their robustness and their ability to exploit the high switching speeds of transistors in scaled technologies [1]. Operating in discrete time also allows for system reconfiguration by changing the sampling frequency. Moreover, different sampling frequencies can be applied throughout a system. This multirate feature can then be exploited to trade performance for power and flexibility. The multirate technique can also be of benefit to discrete-time ∆Σ modulators. In ∆Σ modulators, the first integrators are the largest contributors to the overall power consumption since they set the overall noise and distortion of the modulator. Th

👥 作者与机构

Lynn Bos1,2, Gerd Vandersteen2, Julien Ryckaert1, Pieter Rombouts3,