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本文提出了一种在0.13µm CMOS工艺下实现的两步流水线ADC，工作电压1.2V，采样率30MS/s，SNDR达到70.4dB。通过优化两级级联增益级的组合，显著降低了功耗，实现了31.3fJ/转换步的品质因数，解决了低功耗与高性能之间的矛盾。
National Semiconductor, Santa Clara, CA which may be done simply by changing the gain combination in the two cascaded gain stages. Such optimization may lead to further reduction in power consumption and also allow for lower supply operation well beyond 1.2V. To verify the idea, a 14b 2-step pipelined ADC is implemented and the test result demonstrates an FoM of 31.3fJ/conversion-step. 1 2 Analog-to-digital conversion with a signal bandwidth of 10 to 20MHz and ENOB of 11 to 12b has become a common requirement in many modern wireless communication systems where low power consumption is always a necessity. Typically, the traditional 2-step pipelined ADC is not considered a good candidate to meet these design specifications, since it is implemented with a power-hungry high-resolution flash sub-ADC and high-gain residue amplifier. Recently, however, low-power SAR architectures have been proposed as efficient replacements for flash-based sub-ADCs [1], especially since the conversion rate ma
Ho-Young Lee1, Bumha Lee2, Un-Ku Moon1
Oregon State University, Corvallis, OR