An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs

📋 论文概要

该论文提出了一种基于LC带通ΔΣ调制器的ADC，采用CMOS DACs，在20MHz带宽内实现了70dB SNDR。该设计避免了直接变频接收机中的IQ不平衡、二阶互调等问题，适用于低功耗IEEE 802.11n接收机，使用固定3.2GHz时钟和700-800MHz中频。

💡 主要创新点

• 采用LC带通ΔΣ架构，结合CMOS DACs，在20MHz带宽内实现70dB SNDR，避免了传统直接变频接收机的性能退化。
• 使用固定3.2GHz时钟和整数N PLL，简化了LO生成，降低了功耗和相位噪声。

🏷 关键词

📄 原文摘要

avoids the traditional problems of direct-conversion receivers, such as EVM degradation due to IQ imbalance, 2nd-order intermodulation, and AGC interaction with DC offset correction settling. Our target application is a low-power IEEE 802.11n receiver for 2.4 to 2.5GHz using a fixed 3.2GHz clock and IF tuned from 700 to 800MHz (see Fig. 8.1.1). The fixed clock allows an integer-N PLL with high reference frequency (40MHz, for example), which allows wide loop bandwidth and low phase noise, even at mW-level power consumption (e.g. [1]). The power savings from simplified LO generation are also important. Sampling from IF with an fs/4 modulator rather than sampling from RF with a 3fs/4 modulator (as in [2]) gives higher ADC SNR because Q-enhanced LC filters have a tradeoff between Q and SNR

👥 作者与机构

Jeffrey Harrison1, Michal Nesselroth1, Robert Mamuad1, Arya Behzad2,

Andrew Adams1, Steve Avery1 Broadcom, Sydney, Australia Broadcom, San Diego, CA 1 2 Digitization from IF or RF using an LC bandpass ΔΣ modulator