A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators

📋 论文概要

该论文提出了一种基于开关环形振荡器的高度数字化时间-数字转换器（TDC），实现了13位分辨率、315fsrms抖动、2mW功耗和500MS/s采样率，带宽为1MHz。解决了传统TDC分辨率受限于工艺门延迟以及流水线TDC中时间残差放大器非线性难以控制的问题。

💡 主要创新点

• 采用开关环形振荡器结构，实现了高分辨率、低功耗的全数字TDC设计。
• 通过数字技术克服了传统TDC中模拟电路的非线性问题，提高了鲁棒性。
• 在500MS/s采样率下达到13位有效位数，同时功耗仅2mW，性能功耗比优异。

🏷 关键词

📄 原文摘要

Time-to-digital converters (TDCs) were historically used in laser range-finding, automatic test equipment, and timing jitter measurements, but recent developments in the design of high-resolution TDCs have paved the way for mostly digital implementation of PLLs and ADCs. Among the state-of-the-art TDCs, a flash TDC is the simplest, but its resolution is technology-limited by the minimum gate delay [1]. A pipelined TDC overcomes the technology limitation, but the characteristics of the inter-stage time-residue amplifier are inherently nonlinear and are therefore difficult to control in a robust manner [2]. A MASH TDC can improve the resolution by leveraging oversampling and noise shaping, but extracting the quantization error in the time domain poses many challenges [3]. A single-loop phase-domain continuous-time (CT) ΔΣ in [4] is susceptible to analog circuit imperfections. Furthermore, sampling frequency, FS, in all previous TDCs must be equal to the input carrier frequency, FC, which

👥 作者与机构

Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu

Oregon State University, Corvallis, OR